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## Project description
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## Project description
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**BabyWR** is a cost effective and small pluggable WR node. BabyWR has a a [M.2 form-factor](https://members.pcisig.com/wg/PCI-SIG/document/folder/838). BabyWR was designed for low phase noise timing generation. For applications that demand ultimate phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR** is a cost effective and small pluggable WR node. BabyWR has a a [M.2 form-factor](https://members.pcisig.com/wg/PCI-SIG/document/folder/838). BabyWR was designed for low phase noise (10 MHz; -105 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card that can except a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card that can except a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface.
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... | @@ -12,58 +12,40 @@ _Figure 1: Preliminary 3D view of the BabyWR PCB._ |
... | @@ -12,58 +12,40 @@ _Figure 1: Preliminary 3D view of the BabyWR PCB._ |
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## Main Features
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## Main Features
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- M.2 Type 22 60-D6-M
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- M.2 Type 22 60-D6-M
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- Form-factor 22x60 mm
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- Form-factor 22x60 mm
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- Key-M (Socket 3 PCIe-based Adapter)
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- Key-M (Socket 3 PCIe-based Adapter)
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- PCIex1 Gen4
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- PCIex1 Gen4
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
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- 12 GTH (1 used for PCIe, 1 used for SFP)
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- 12 GTH (1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via W.FL coax or M.2 connector)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via W.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-125.000 MHz DCTCXO WR local reference clock
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-124.992 MHz DCTCXO WR dmtd helper clock
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via W.FL connectors (3, 4)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via W.FL connectors (3, 4)
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- On board memory
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- On board memory
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
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- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
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- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
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- Miscellaneous
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- Miscellaneous
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- 4x W.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
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- 4x W.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
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- JTAG interface via M.2 connector pins
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- JTAG interface via M.2 connector pins
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- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
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- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
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- 10 MHz, 1 PPS differential outputs via M.2 connector pins
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- 10 MHz, 1 PPS differential outputs via M.2 connector pins
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- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
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- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
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- 3 GPIO1V8 lines (can be used for: reset etc.)
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- 3 GPIO1V8 lines (can be used for: reset etc.)
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- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
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- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
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- 4 GPIO LEDs
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- 4 GPIO LEDs
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- 1 LED FPGA configuration DONE
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- 1 LED FPGA configuration DONE
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- SMD 0402 land pattern used as configuration button.
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- SMD 0402 land pattern used as configuration button.
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- 10 layer PCB
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- 10 layer PCB
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- All signals ESD protected
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- All signals ESD protected
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- Power consumption
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- Power consumption
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- 3V3 estimated 1,5 Watt
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- 3V3 estimated 1,5 Watt
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-----
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