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## Project description
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**BabyWR** is being developed as a cost effective and small pluggable WR node. BabyWR has a [M.2 form-factor](https://members.pcisig.com/wg/PCI-SIG/document/folder/838). BabyWR is designed for low phase noise (10 MHz; -105 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR** is being developed as a cost effective and small pluggable WR node. BabyWR has a [M.2 form-factor](https://en.wikipedia.org/wiki/M.2). BabyWR is designed for low phase noise (10 MHz; -105 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card that can except a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface.
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![BabyWR_220701](https://ohwr.org/project/babywr/wikis/uploads/551ac21965a005fb57db6c5ca71df1a2/BabyWR_220701.jpg)
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_Figure 1: Preliminary 3D view of the BabyWR PCB._
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- M.2 Type 22 60-D6-M
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- Form-factor 22x60 mm
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- Key-M (Socket 3 PCIe-based Adapter)
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- PCIex1 Gen4
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- PCIe x1 Gen4
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
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- 12 GTH (1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via W.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/datasheet/SiT5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via W.FL connectors (3, 4)
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- On board memory
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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... | ... | @@ -45,7 +45,7 @@ _Figure 1: Preliminary 3D view of the BabyWR PCB._ |
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## Project information
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- Official production documentation
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- BabyWR Schematics (will be uploaded soon) (Note: Design created with Mentor Graphics using a Xpedition).
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- BabyWR Schematics (will be uploaded soon) (Note: Design created with Mentor Graphics using a Xpedition License).
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- BabyWR Manufacturing files 11300.09.01.2 (will be uploaded soon) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [Frequently Asked Questions](/project/babywr/wikis/FAQ)
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- [VCXOPlayGround_i2c](/project/babywr/wikis/VCXOPlayGround_i2c), a pre-study project was started to test the feasibility of SiTime-5359 I2C controllable DCTCXO
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