... | ... | @@ -17,17 +17,17 @@ _Figure 1: BabyWR PCB._ |
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- PCIe x1 Gen3
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
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- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via W.FL coax or M.2 connector)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via W.FL connectors (3, 4)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (3, 4)
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- On board memory
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
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- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
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- Miscellaneous
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- 4x W.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
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- 4x U.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
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- JTAG interface via M.2 connector pins
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- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
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- 10 MHz, 1 PPS differential outputs via M.2 connector pins
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... | ... | @@ -65,9 +65,9 @@ _Figure 2: BabyWR-Carrier PCB._ |
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- 2x for differential external 125 MHz WR reference clock input from optional high precision external oscillator
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- 2x for differential 10 MHz output clock (or other signal depending on BabyWR configuration)
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- 2x for differential PPS output (or other signal depending on BabyWR configuration)
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- 4x SMA connectors that translate to 4x W.FL connectors
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- 4x W.FL connectors that can connected the BabyWR W.FL connectors via coax
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- access to BabyWR optional external reference clock and RF GPIO (W.FL connectors)
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- 4x SMA connectors that translate to 4x U.FL connectors
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- 4x U.FL connectors that can connected the BabyWR U.FL connectors via coax
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- access to BabyWR optional external reference clock and RF GPIO (U.FL connectors)
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- 1x10 pin header for access programmable BabyWR 3V3 GPIO signals
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- 1x5 pin header for access programmable BabyWR 1V8 GPIO signals
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- 4x 3-pin jumper to select UART or FMC pins for connecting to programmable BabyWR GPIO signals
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... | ... | @@ -86,8 +86,8 @@ _Figure 2: BabyWR-Carrier PCB._ |
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- Official production documentation
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- [BabyWR Schematics](uploads/d3dd3b14852122ba2c5e8ba4596368dd/11300.09.02.1_SCH.PDF) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR Manufacturing files](uploads/069672cac79fbf2d7d9d8ce451c08f9b/11300.09.02.1_PCB.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR-Carrier Schematics](uploads/07fbba67abd921963ef0ff08bce73791/11300.10.02.0_SCH.pdf) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR-Carrier Manufacturing files](uploads/b089553ea51d4de47b3f45b59501a289/11300.10.02.0_PCB.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR-Carrier Schematics](uploads/8c4a2a595b7dced0b65b3dc7d783a3ec/11300.10.02.2_SCH.pdf) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR-Carrier Manufacturing files](uploads/99e9314b92f37264cc9178ef14870545/11300.10.02.2_PCB_Variant-2280.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- Phase Noise performance
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- Although the first prototype BabyWR is fully functional the Phase Noise performance does not meet expectations. Currently a design study is ongoing to mitigate this issue. The next iteration of BabyWR will probably have a 22x80 mm M.2 form-factor (instead of 22x60 mm)
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- Read more about [Artix Ultrascale+ Phase Noise performance measurements](Phase_Noise_performance).
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