|
|
# Reference Design Catalog
|
|
|
|
|
|
\> Follow this link to access the [full project
|
|
|
repository](https://www.ohwr.org/project/asyncart/wikis/documents)
|
|
|
The original work conducted over FPGAs the AsyncArt project was targeted to Xilinx devices, specifically:
|
|
|
- Virtex-4 XC4VFX20: [Xilinx ML405](https://www.xilinx.com/support/documentation/boards_and_kits/ug210.pdf)
|
|
|
- Spartan-3 XC3S200: [Xilinx Spartan-3 Starter Kit](https://www.xilinx.com/support/documentation/boards_and_kits/ug130.pdf)
|
|
|
|
|
|
The collection of demo examples from the AsyncArt project was made publicly available in the date of 2012/12/27, and you will need the following FPGA toolchain to open, explore and rebuild them:
|
|
|
|
|
|
- **Integrated Design Environment:** [Xilinx ISE
|
|
|
Webpack 14](http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm),
|
|
|
the industry´s only FREE, fully featured front-to-back FPGA design
|
|
|
solution for Linux, Windows XP, and Windows 7. ISE WebPACK is the
|
|
|
ideal downloadable solution for FPGA and CPLD design offering HDL
|
|
|
synthesis and simulation, implementation, device fitting, and JTAG
|
|
|
programming.
|
|
|
|
|
|
The AsyncArt project deriverables are then compressed full Xilinx ISE
|
|
|
projects, all of them consisting in two fundamental blocks:
|
|
|
|
|
|
- **TOP-Level Schematic**: when dealing with asynchronous design,
|
|
|
being conscious of the dynamics and geometry of critical signal
|
|
|
paths is a key issue. By this reason, the AsyncArt reference designs
|
|
|
are released as visually descriptive schematics files.
|
|
|
|
|
|
\> ***Design tip:** hierachy is critical when synthesizing an
|
|
|
asynchronous design. For a successful synthesis, Keep Hierachy property
|
|
|
should be enabled.*
|
|
|
|
|
|
- **HDL TestBench**: as a quick-start to real work, with every
|
|
|
schematic is attached a testbench ready to be simulated. This
|
|
|
testbench contains information related to the input operation &
|
|
|
purpose and the output that should be observed.
|
|
|
|
|
|
\> ***Design tip:** Real world delays are the big deal with asynchronous
|
|
|
logic. For a successful simulation, Post Place & Route models should be
|
|
|
used.*
|
|
|
|
|
|
*NOTE:** A single design deliverable may contain more than one
|
|
|
schematic/testbench pair
|
|
|
|
|
|
|
|
|
## Library
|
|
|
|
... | ... | |