... | ... | @@ -60,7 +60,7 @@ them to a free to use project development environment. |
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By date of 2012/12/27, the development environment is comprised by:
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- Operative System: [Scientific
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- **Operative System:** [Scientific
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Linux 6](https://www.scientificlinux.org/), a Linux release put
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together by Fermilab, CERN, and various other labs and universities
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around the world. Its primary purpose is to reduce duplicated effort
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... | ... | @@ -72,7 +72,7 @@ By date of 2012/12/27, the development environment is comprised by: |
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<!-- end list -->
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- Integrated Design Environment: [Xilinx ISE
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- **Integrated Design Environment:** [Xilinx ISE
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Webpack 14](http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm),
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the industry´s only FREE, fully featured front-to-back FPGA design
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solution for Linux, Windows XP, and Windows 7. ISE WebPACK is the
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... | ... | @@ -83,21 +83,23 @@ By date of 2012/12/27, the development environment is comprised by: |
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The AsyncArt project deriverables are then compressed full Xilinx ISE
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projects, all of them consisting in two fundamental blocks:
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- TOP-Level Schematic: when dealing with asynchronous design, being
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conscious of the dynamics and geometry of critical signal paths is a
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key issue. By this reason, the AsyncArt reference designs are
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released as visually descriptive schematics files.
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- **TOP-Level Schematic**: when dealing with asynchronous design,
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being conscious of the dynamics and geometry of critical signal
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paths is a key issue. By this reason, the AsyncArt reference designs
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are released as visually descriptive schematics files.
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\> ***Design tip:** hierachy is critical when synthesizing an
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asynchronous design. For a successful synthesis, Keep Hierachy property
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must be enabled.*
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should be enabled.*
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- HDL TestBench: as a quick-start to real work, with every schematic
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is attached a testbench ready to be simulated.
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- **HDL TestBench**: as a quick-start to real work, with every
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schematic is attached a testbench ready to be simulated. This
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testbench contains all the information related to the input
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operation & purpose and the output that should be observed.
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\> \_**Design tip:** Real world delays are the big deal with
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asynchronous logic. For a successful simulation, post place & route
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models must be used.
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\> ***Design tip:** Real world delays are the big deal with asynchronous
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logic. For a successful simulation, Post Place & Route models should be
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used.*
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*NOTE:** A single deliverable may contain more than one
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schematic/testbench pair
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