... | @@ -21,7 +21,7 @@ Another solution is to use a **GALS design style**: there are different (e.g. ph |
... | @@ -21,7 +21,7 @@ Another solution is to use a **GALS design style**: there are different (e.g. ph |
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# Technical Details
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# Technical Details
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The original AsyncArt research project was conducted by **Javier Garcia-Lasheras** between 2005 and 2007 with the support of the **Communication, Signal and Microwaves group** of the [Public University of Navarre](https://www.unavarra.es/?languageId=1). The target for this research was to demonstrate the advantages of a full featured System-on-Chip ASIC implemented with the GALS approach. After heavy testing in FPGAs, an **ASIC chip dubbed PNX-2006** was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques.
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The original AsyncArt research project was conducted by **Javier Garcia-Lasheras** between 2005 and 2007 with the support of the **Communication, Signal and Microwaves group** of the [Public University of Navarre](https://www.unavarra.es/?languageId=1). The target for this research was to demonstrate the **advantages of a full featured System-on-Chip ASIC implemented with the GALS approach**. After heavy testing in FPGAs, an **ASIC chip dubbed PNX-2006** was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques.
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During the research, we noticed that **the FPGA prototypes performed very close to the physical limit of the technology** while incurring in a **very low logic overhead**. Indeed, they performed far better than the PNX-2006, because while the foundry we used for **the ASIC was based on 0.5 micrometer CMOS process, the FPGA devices for the prototypes were based on 45 and 90 nanometers processes**. In order to allow further research on this topic, we published the **internal technical details for our GALS implementation for FPGAs** in the following paper:
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During the research, we noticed that **the FPGA prototypes performed very close to the physical limit of the technology** while incurring in a **very low logic overhead**. Indeed, they performed far better than the PNX-2006, because while the foundry we used for **the ASIC was based on 0.5 micrometer CMOS process, the FPGA devices for the prototypes were based on 45 and 90 nanometers processes**. In order to allow further research on this topic, we published the **internal technical details for our GALS implementation for FPGAs** in the following paper:
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