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# Description
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# Description
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The AsyncArt Project is comprised by a set of Open-Source HDL libraries
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targeted to the efficient implementation of clockless/asynchronous
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circuits over Commercial-Off-The-Shelf devices & technologies.
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Even the fact that the design approach
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It's worthy to note that, more than a standard library, the core of the
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AsyncArt project is a collection of very simple reference design
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examples that contain useful tricks and methodologies that can be easily
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extrapolated to more complex projects.
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# Prerequisites
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# Prerequisites
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\_Asynchronous macro-modules were a Pain to Build but a Joy to Use
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\_Asynchronous macro-modules were a Pain to Build but a Joy to Use
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... | @@ -45,5 +56,20 @@ FPGAs is shared in some way or another by all of them. |
... | @@ -45,5 +56,20 @@ FPGAs is shared in some way or another by all of them. |
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# Licensing
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# Licensing
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The licensing policy of the AsyncArt project is quite simple and can be
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resumed in the nexts facts:
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- You are granted to use the HDL code provided as a IP-Core library in
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any design, and by doing this you are not forced to disclose the
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other IP-Cores involved in the system.
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- If you change or improve the HDL code in any way, you must share
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your modifications with the open-source design community.
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It's a fair deal, isn't it?
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To clarify the licensing terms, we have chosen the LGPLv2.0 license, the
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most optimal available one, in order to fullfill the previous facts in a
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satisfactory way
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# Loose Ends
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# Loose Ends
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