... | @@ -64,10 +64,10 @@ series was republished in the [EETimes](http://www.eetimes.com) in 2014: |
... | @@ -64,10 +64,10 @@ series was republished in the [EETimes](http://www.eetimes.com) in 2014: |
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In order to allow for a widespread testing and potential adoption of the technology by community, we first worked in migrating the reference designs to FPGA devices from other vendors. In this way, we verified that the asynchronous logic circuitry in **the AsyncArt GALS approach works on devices from Xilinx, Intel (formerly Altera), Microsemi (formerly Actel) and Lattice**.
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In order to allow for a widespread testing and potential adoption of the technology by community, we first worked in migrating the reference designs to FPGA devices from other vendors. In this way, we verified that the asynchronous logic circuitry in **the AsyncArt GALS approach works on devices from Xilinx, Intel (formerly Altera), Microsemi (formerly Actel) and Lattice**.
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In all of the cases, the main of the problems at the time of applying the GALS approach to complex SoC designs are related with the obscurity and lack of the required fine-grained control in the proprietary FPGA synthesis and floorplanning toolchains.
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In all of the cases, the main of the problems at the time of applying the GALS approach to complex SoC designs are related with the **obscurity and lack of the required fine-grained control in the proprietary FPGA toolchains**. When dealing with GALS, you need to check **different critical paths and clock constraints for several design regions**, and this is not always possible with proprietary tools.
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For this reason, **we are currently migrating the designs to a 100% FLOSS FPGA toolchain**, based on [Project IceStorm](http://www.clifford.at/icestorm/), [Yosys](http://www.clifford.at/yosys/) and [Nextpnr](https://github.com/YosysHQ/nextpnr). In this way, in the repository you will find the **VHDL and Verilog version** of simple asynchronous cells and a series of **practical examples** based on the [Lattice iCEstick Evaluation Kit](https://www.latticesemi.com/icestick)
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For this reason, **we are currently migrating the designs to a 100% FLOSS FPGA toolchain**, based on [Project IceStorm](http://www.clifford.at/icestorm/), [Yosys](http://www.clifford.at/yosys/) and [Nextpnr](https://github.com/YosysHQ/nextpnr). In this way, in the repository you will find the **VHDL and Verilog version** of simple asynchronous cells and a series of **practical examples** based on the [Lattice iCEstick Evaluation Kit](https://www.latticesemi.com/icestick)
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Currently, **only the basic micropipeline demo is available** but this is a very good entry point to implementing asynchronous logic circuits in general and GALS in particular. By studying the micropipeline, you can check how fast your async design will be able to run and how physical effects affect to the speed of the CMOS circuitry, e.g.:
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Currently, **only the basic micropipeline demo is available** but this is a very good entry point to implementing asynchronous logic circuits in general and GALS in particular. By studying the micropipeline, you can check how fast your async design will be able to run and how physical derives have an impact in the speed of the CMOS circuitry, e.g.:
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- The more the supply voltage is, the faster the circuit runs.
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- The more the supply voltage is, the faster the circuit runs.
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- The lower the die temperature is, the faster the circuit runs. |
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- The lower the die temperature is, the faster the circuit runs. |