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... | @@ -79,65 +79,6 @@ use since 2006). |
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- [Asynchronous circuit design - A
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- [Asynchronous circuit design - A
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tutorial](http://www2.imm.dtu.dk/pubdb/views/publication_details.php?id=855)
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tutorial](http://www2.imm.dtu.dk/pubdb/views/publication_details.php?id=855)
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# Demonstrative reference designs
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\> Follow this link to access the
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[Reference-Design-Catalog](Reference-Design-Catalog)
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As noted before, more than a standard HDL library, the AsyncArt project
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contains a collection of demonstrative reference designs that contains
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tricks and blocks than can be easily reused.
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In order to make easier the use of this techniques for educative
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purposes, the released reference designs has been standarized by porting
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them to a free to use project development environment.
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By date of 2012/12/27, the development environment is comprised by:
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- **Operative System:** [Scientific
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Linux 6](https://www.scientificlinux.org/), a Linux release put
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together by Fermilab, CERN, and various other labs and universities
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around the world. Its primary purpose is to reduce duplicated effort
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of the labs, and to have a common install base for the various
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experimenters. The base SL distribution is basically Enterprise
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Linux, recompiled from source. The main goal for the base
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distribution is to have everything compatible with Enterprise, with
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only a few minor additions or changes.
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<!-- end list -->
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- **Integrated Design Environment:** [Xilinx ISE
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Webpack 14](http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm),
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the industry´s only FREE, fully featured front-to-back FPGA design
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solution for Linux, Windows XP, and Windows 7. ISE WebPACK is the
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ideal downloadable solution for FPGA and CPLD design offering HDL
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synthesis and simulation, implementation, device fitting, and JTAG
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programming.
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The AsyncArt project deriverables are then compressed full Xilinx ISE
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projects, all of them consisting in two fundamental blocks:
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- **TOP-Level Schematic**: when dealing with asynchronous design,
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being conscious of the dynamics and geometry of critical signal
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paths is a key issue. By this reason, the AsyncArt reference designs
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are released as visually descriptive schematics files.
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\> ***Design tip:** hierachy is critical when synthesizing an
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asynchronous design. For a successful synthesis, Keep Hierachy property
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should be enabled.*
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- **HDL TestBench**: as a quick-start to real work, with every
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schematic is attached a testbench ready to be simulated. This
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testbench contains information related to the input operation &
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purpose and the output that should be observed.
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\> ***Design tip:** Real world delays are the big deal with asynchronous
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logic. For a successful simulation, Post Place & Route models should be
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used.*
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*NOTE:** A single design deliverable may contain more than one
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schematic/testbench pair
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# Licensing
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# Licensing
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The licensing policy of the AsyncArt project is quite simple and can be
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The licensing policy of the AsyncArt project is quite simple and can be
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