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... | @@ -29,9 +29,9 @@ During the research, we noticed that **the FPGA prototypes performed very close |
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synchronous FPGAs: a new
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synchronous FPGAs: a new
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approach](http://arxiv.org/abs/arXiv:0802.3441)
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approach](http://arxiv.org/abs/arXiv:0802.3441)
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## The first release of AsyncArt
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## The Original Release of AsyncArt
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the **Open Hardware Repository**. Those designs were originally implemented over Xilinx 3th and 4th Series devices, so they were updated to Xilinx 6th Series devices and distributed as a **collection of schematic projects for Xilinx ISE**:
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Five years later, in 2012, **the original FPGA projects that served as prototypes for the PNX-2006 ASIC chip** were published as free/open source in the **Open Hardware Repository**. Those designs were implemented over *Xilinx 3th and 4th Series* devices, so they were updated to *Xilinx 6th Series* devices and distributed as a **collection of schematic projects for Xilinx ISE**:
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- [Complete AsyncArt project collection for Xilinx ISE](Reference-Design-Catalog)
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- [Complete AsyncArt project collection for Xilinx ISE](Reference-Design-Catalog)
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As a companion for this project collection, an **AsyncArt Quick-Start** was originally published as a blog series on
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As a companion for this project collection, an **AsyncArt Quick-Start** was originally published as a blog series on
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