... | ... | @@ -8,9 +8,9 @@ design architectures over Commercial-Off-The-Shelf FPGA devices. |
|
|
|
|
|
A GALS circuit consists of a set of **locally synchronous modules** communicating with each other via asynchronous wrappers. In this way, each synchronous subsystem ("clock domain") can run on its own locally generated independent clock (frequency), while sharing data with their neighboring modules by using **asynchronous micropipelines**.
|
|
|
|
|
|
One of the critical **advantages of GALS** over pure synchronous designs is the **much lower electromagnetic interference (EMI)**. The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialized by an active clock edge. Therefore, large spikes on supply current occur at active clock edges. These spikes can cause large electromagnetic interference, and may ultimately lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used, but this is not always possible and no more than hack for the actual problem.
|
|
|
One of the critical **advantages of GALS** over pure synchronous designs is the **much lower electromagnetic interference (EMI)**. The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialized by an active clock edge. Therefore, **large spikes on supply current occur at active clock edges in synchronous designs**. These spikes can cause large electromagnetic interference, and may ultimately lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used, but this is not always possible and no more than hack for the actual problem.
|
|
|
|
|
|
Another solution is to use a GALS design style: there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus supply current spikes do not aggregate at the same time. Consequently, GALS design style is often used in system-on-a-chip (SoC), being of special interest for Network-on-Chip (NoC) based architectures.
|
|
|
Another solution is to use a **GALS design style**: there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus **supply current spikes do not aggregate at the same time**. Consequently, GALS design style is often used in system-on-a-chip (SoC), being of special interest for Network-on-Chip (NoC) based architectures.
|
|
|
|
|
|
- [Text derived from the GALS entry at Wikipedia](https://en.wikipedia.org/wiki/Globally_asynchronous_locally_synchronous)
|
|
|
|
... | ... | @@ -21,7 +21,7 @@ AsyncArt project is a **collection of very simple reference design |
|
|
examples** that contain useful tricks and methodologies that can be **easily
|
|
|
extended to more complex projects**.
|
|
|
|
|
|
The [complete project collection](Reference-Design-Catalog) from the original AsyncArt research work in 2005-2007 was conducted over Xilinx devices and was released in 2012 as a collection of schematic projects for a more visually-oriented design:
|
|
|
The [complete project collection](Reference-Design-Catalog) from the original AsyncArt research work in 2005-2007 was conducted over Xilinx devices and was released in 2012 as a collection of schematic projects for a more visually-oriented design.
|
|
|
|
|
|
# Learning Resources
|
|
|
|
... | ... | |