... | @@ -21,33 +21,18 @@ AsyncArt project is a **collection of very simple reference design |
... | @@ -21,33 +21,18 @@ AsyncArt project is a **collection of very simple reference design |
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examples** that contain useful tricks and methodologies that can be **easily
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examples** that contain useful tricks and methodologies that can be **easily
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extended to more complex projects**.
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extended to more complex projects**.
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The original AsyncArt research project was conducted by **Javier Garcia-Lasheras** between 2005 and 2007 with the support of the **Communication, Signal and Microwaves group** of the [Public University of Navarre](https://www.unavarra.es/?languageId=1). The target for this research was to demonstrate the advantages of a full featured System-on-Chip ASIC implemented with the GALS approach. After heavy testing in FPGAs, an ASIC chip dubbed PNX-2006 was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques in the synchronous blocks.
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The original AsyncArt research project was conducted by **Javier Garcia-Lasheras** between 2005 and 2007 with the support of the **Communication, Signal and Microwaves group** of the [Public University of Navarre](https://www.unavarra.es/?languageId=1). The target for this research was to demonstrate the advantages of a full featured System-on-Chip ASIC implemented with the GALS approach. After heavy testing in FPGAs, an ASIC chip dubbed PNX-2006 was successfully built, demonstrating Asynchronous Network-on-Chip capabilities and active power consumption and EM interference reduction techniques.
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were implemented over Xilinx devices and are distributed as a collection of schematic projects for **Xilinx ISE**. You can find the collection with the original example projects in this link:
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During the research, we noticed that the FPGA prototypes performed very close to the physical limit of the technology while incurring in a very low logic overhead. Being aware of this being a major breakthrough, we published the internal details for our GALS implementation in the following paper:
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- [Complete project collection for ISE](Reference-Design-Catalog)
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# Learning Resources
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**Asynchronous macro-modules were a Pain to Build but a Joy to Use**
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*Wesley A. Clark*
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Asynchronous logic design may be a very hard subject. In order to fully
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understand the power of this kind of design and its potential advantages
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over the traditional synchronous paradigm, relatively some theoretical
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foundations and practical skills should be previously acquired.
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## The AsyncArt asynchronous design approach
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The subtle design tricks & details present in the AsyncArt reference designs will be clear
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enough after reading the next paper:
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- [Efficient implementation of GALS systems over commercial
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- [Efficient implementation of GALS systems over commercial
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synchronous FPGAs: a new
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synchronous FPGAs: a new
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approach](http://arxiv.org/abs/arXiv:0802.3441)
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approach](http://arxiv.org/abs/arXiv:0802.3441)
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Is important to note that the concrete approach introduced in this paper
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only covers a limited set of the presented reference designs, but the
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were implemented over Xilinx devices and are distributed as a collection of schematic projects for **Xilinx ISE**. You can find the collection with the original example projects in this link:
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core signaling mechanism is shared in one way or another by all of them.
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- [Complete project collection for ISE](Reference-Design-Catalog)
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## AsyncArt blog series
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## AsyncArt blog series
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... | @@ -76,19 +61,6 @@ series was republished in the [EETimes](http://www.eetimes.com): |
... | @@ -76,19 +61,6 @@ series was republished in the [EETimes](http://www.eetimes.com): |
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- Here we see a suite of circuits that demonstrate different
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- Here we see a suite of circuits that demonstrate different
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aspects of asynchronous micropipelines.
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aspects of asynchronous micropipelines.
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## Further reading
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There are plenty of educative material online about asynchronous logic
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design, but there is a little gem than shines over the rest of available
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books, papers or tutorials. This gem is the book *Principles of
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asynchronous circuit design - A systems perspective*, published in 2001
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by [Jens Sparsoe](http://www2.imm.dtu.dk/~jspa/) & [Steve
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Furber](http://en.wikipedia.org/wikis/Steve_Furber) (more precisely, the
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chapters 1-8 by Sparsoe, freely available for non-commercial educational
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use since 2006).
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- [Asynchronous circuit design - A
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tutorial](http://www2.imm.dtu.dk/pubdb/views/publication_details.php?id=855)
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# Licensing
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# Licensing
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