... | ... | @@ -64,5 +64,8 @@ series was republished in the [EETimes](http://www.eetimes.com) in 2014: |
|
|
|
|
|
In order to allow for a widespread testing and potential adoption of the technology by community, we first worked in migrating the reference designs to FPGA devices from other vendors. In this way, we verified that the asynchronous logic circuitry in **the AsyncArt GALS approach works on devices from Xilinx, Intel (formerly Altera), Microsemi (formerly Actel) and Lattice**.
|
|
|
|
|
|
In all of the cases, the main of the drawbacks at the time of applying the GALS approach was related with the obscurity and lack of the required fine-grained control in the proprietary FPGA synthesis and floorplanning toolchains.
|
|
|
In all of the cases, the main of the problems at the time of applying the GALS approach to complex SoC designs are related with the obscurity and lack of the required fine-grained control in the proprietary FPGA synthesis and floorplanning toolchains.
|
|
|
|
|
|
For this reason, we are currently migrating the designs to a 100% FLOSS FPGA toolchain, based on Project IceStorm, Yosys and Nextpnr. In this way, in the repository you will find the **VHDL and Verilog version** of simple asynchronous cells and a series of **practical examples** based on the [Lattice iCEstick Evaluation Kit](https://www.latticesemi.com/icestick)
|
|
|
|
|
|
- **NOTE:** currently, only the basic micropipeline demo is available. |