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## The first release of AsyncArt
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were originally implemented over Xilinx 3th and 4th Series devices, so they were updated to Xilinx 6th Series devices and distributed as a collection of schematic projects for **Xilinx ISE**. You can find the collection with the original example projects in this link:
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- [Complete project collection for ISE](Reference-Design-Catalog)
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the **Open Hardware Repository**. Those designs were originally implemented over Xilinx 3th and 4th Series devices, so they were updated to Xilinx 6th Series devices and distributed as a **collection of schematic projects for Xilinx ISE**:
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- [Complete AsyncArt project collection for Xilinx ISE](Reference-Design-Catalog)
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An **AsyncArt Quick-Start** was originally published as a blog series on
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[All Programmable Planet](http://www.programmableplanet.com/) in 2013, an online
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# Current research
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In order to allow for a widespread testing and potential adoption of the technology by community, we first worked in migrating the reference designs to FPGA devices from other vendors. In this way, we verified that the asynchronous logic circuitry in **the AsyncArt GALS approach works on devices from Xilinx, Intel (formerly Altera), Microsemi (formerly Actel) and Lattice**.
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In all of the cases, the main of the drawbacks at the time of applying the GALS approach was related with the obscurity and lack of the required fine-grained control in the proprietary FPGA synthesis and floorplanning toolchains.
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