... | @@ -68,5 +68,5 @@ In all of the cases, the main of the problems at the time of applying the GALS a |
... | @@ -68,5 +68,5 @@ In all of the cases, the main of the problems at the time of applying the GALS a |
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For this reason, **we are currently migrating the designs to a 100% FLOSS FPGA toolchain**, based on [Project IceStorm](http://www.clifford.at/icestorm/), [Yosys](http://www.clifford.at/yosys/) and [Nextpnr](https://github.com/YosysHQ/nextpnr). In this way, in the repository you will find the **VHDL and Verilog version** of simple asynchronous cells and a series of **practical examples** based on the [Lattice iCEstick Evaluation Kit](https://www.latticesemi.com/icestick).
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For this reason, **we are currently migrating the designs to a 100% FLOSS FPGA toolchain**, based on [Project IceStorm](http://www.clifford.at/icestorm/), [Yosys](http://www.clifford.at/yosys/) and [Nextpnr](https://github.com/YosysHQ/nextpnr). In this way, in the repository you will find the **VHDL and Verilog version** of simple asynchronous cells and a series of **practical examples** based on the [Lattice iCEstick Evaluation Kit](https://www.latticesemi.com/icestick).
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**NOTE**: Currently, only the basic [micropipeline demo](micropipeline_demo) is available, but this is a very good entry point to implementing **asynchronous logic circuits in general and GALS in particular**.
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**NOTE**: Currently, only the basic [micropipeline demo](micropipeline-demo) is available, but this is a very good entry point to implementing **asynchronous logic circuits in general and GALS in particular**.
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