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synchronous FPGAs: a new
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approach](http://arxiv.org/abs/arXiv:0802.3441)
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## Original reference designs
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## The first release of AsyncArt
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Five years later, in 2012, the experimental FPGA projects that served as prototypes for the PNX-2006 ASIC chip were published as free/open source in the Open Hardware Repository. Those designs were implemented over Xilinx devices and are distributed as a collection of schematic projects for **Xilinx ISE**. You can find the collection with the original example projects in this link:
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- [Complete project collection for ISE](Reference-Design-Catalog)
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## AsyncArt blog series
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### AsyncArt Quick-Start
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An AsyncArt Quick-Start was originally published as a blog series on
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[All Programmable Planet](http://www.programmableplanet.com/), an online
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aspects of asynchronous micropipelines.
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# Licensing
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The licensing policy of the AsyncArt project is quite simple and can be
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resumed in the nexts facts:
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- You are granted to use the HDL code provided as a IP-Core library in
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any design, and by doing this you are not forced to disclose the
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other IP-Cores involved in the system.
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<!-- end list -->
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- If you change or improve the HDL code in any way, you must share
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your modifications with the open-source design community.
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To clarify the licensing terms, we have chosen the LGPLv2.0 license, the
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most optimal available one, in order to fullfill the previous facts in a
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satisfactory way.
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# Current research |