Absolute Encoder VHDL core
Project description
The absolute encoder package (absenc_pkg) implements components for absolute encoder masters and slaves. It supports the following interfaces:
- ENDAT: https://www.heidenhain.de/de_EN/fundamentals/interfaces/endat-22/
- BISS: https://en.wikipedia.org/wikis/BiSS_interface
- SSI: https://en.wikipedia.org/wikis/Synchronous_Serial_Interface
This implementation is optimized for applications that can be dynamically configured to use one amongst different types of interfaces at a particular time. As much as possible, resources that can be shared across interfaces are factorized (counters, comparators, shift registers ...) and accessed through a multiplexer. However, and in order to avoid penalizing simpler applications, static configuration allows to exclude resources associated with an unused interface.
The master implements the following data conversion pipeline:
/uploads/75b200dcd91a60f80c2349aa340f53a3/absenc_arch.png
master pipeline*
Main features
- Applicable to all interfaces
- master and slave modes
- configurable master clock frequency
- configurable data length
- static timeout
- ENDAT
- send position mode version 2.1 only
- no CRC check
- BISS
- point to point configuration only
- no interleaved bit support (ie. CDS, CDM)
- SSI
- optional gray data coding (master only)
- optional parity bit (not checked)
Project information
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Project Status
Date | Event |
01-10-2015 | Start working on project. |
03-11-2015 | First stable version. |
3 November 2015