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Absolute Encoder VHDL core
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Absolute Encoder VHDL core
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f03ada91
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f03ada91
authored
Feb 22, 2016
by
Fabien Le Mentec
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doc: HSSL
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@@ -105,6 +105,11 @@ The master implements the following data conversion pipeline:
\item
optional gray data coding (master only),
\item
optional parity bit (not checked).
\end{itemize}
\item
HSSL
\begin{itemize}
\item
reader only,
\item
stand alone, no master or slave interface.
\end{itemize}
\end{itemize}
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