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conv-common-gw
Commit eb610e84 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Implementation post-review. Main changes are to pull the falling and rising… 

Implementation post-review. Main changes are to pull the falling and rising edges of the asynch pulses directly from the conv_pulse_gen module as outputs and input those the burst controller. The top files have been modified accordingly. Also the pulse output now is correctly generated at the poutput port depending on PCB version and pulse width selection
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modules/conv_dyn_burst_ctrl.vhd
View file @ eb610e84
--============================================================================== --==============================================================================
-- CERN (BE-CO-HT) -- CERN (BE-CO-HT)
-- Burst mode control module -- Burst mode control module
-- Copyright CERN 2017
--============================================================================== --==============================================================================
-- --
-- author: Denia Bouhired (denia.bouhired@cern.ch) -- author: Denia Bouhired (denia.bouhired@cern.ch)
...@@ -10,11 +11,30 @@ ...@@ -10,11 +11,30 @@
-- version: 1.0 -- version: 1.0
-- --
-- Description: -- Description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, depending on the frequency, the module will allow the pulse to go through for a pre-defined amount of time, before going into pulse rejection mode. The rejection lasts for the time it takes for the "temperature" to go below the set upper limit g_max_temp. -- This module serves as a burst mode controller. When pulses of
--For each frequency, the time of failure selected corresponds to the time it takes to reach g_max_temp for pulses at the same frequency. This is mapped onto the temperature rise caused by a single pulse (the maximum rise at 2MHz max frequency is g_1_pulse_temp_rise) of the corresponding period. The array of values representing the thermal properties at the pulse level is given as the array of integers temp_decre_step. -- pre-defined length (250 ns) arrive, depending on the frequency, the
--This array of values is generated in pre-processing via python script (Link??). These values correspond to the thermal model of the board components defined at the pulse level. -- module will allow the pulse to go through for a pre-defined amount of
-- time, before going into pulse rejection mode. The rejection lasts for
-- the time it takes for the "temperature" to go below the set upper limit
-- g_max_temp. For each frequency, the time of failure selected
-- corresponds to the time it takes to reach g_max_temp for pulses at the
-- same frequency. This is mapped onto the temperature rise caused by a
-- single pulse (the maximum rise at 2MHz max frequency is
-- g_1_pulse_temp_rise) of the corresponding period. The array of values
-- representing the thermal properties at the pulse level is given as the
-- array of integers temp_decre_step. This array of values is
-- generated in pre-processing via python script (Link??). These values
-- correspond to the thermal model of the board components defined at
-- the pulse level.
-- Any modification to the board specification which would change the
-- high frequency operation behaviour, would require changing the 3
-- parameters g_1_pulse_temp_rise, g_max_temp and t_temp_decre_step. These
-- are generated using the Python file (link?)
-- Any modification to the board specification which would change the high frequency operation behaviour, would require changing the 3 parameters g_1_pulse_temp_rise, g_max_temp and t_temp_decre_step. These are generated using the Python file (link?)
-- dependencies: -- dependencies:
-- --
...@@ -31,14 +51,8 @@ ...@@ -31,14 +51,8 @@
-- received a copy of the GNU Lesser General Public License along with this -- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--============================================================================== --==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
-- 11-01-2017 Denia Bouhired Small modifications to improve code.
-- 15-01-2017 Denia Bouhired Now using 2 FSMs for states and outputs.
-- 23-01-2017 Denia Bouhired Changed temp_decrement_step from signal to generic, to allow module to run for different width pulses.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
...@@ -47,21 +61,24 @@ use work.gencores_pkg.all; ...@@ -47,21 +61,24 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all; use work.conv_common_gw_pkg.all;
--============================================================================
--ENTITY DECLARATION
--============================================================================
entity conv_dyn_burst_ctrl is entity conv_dyn_burst_ctrl is
generic generic
( (
-- Fixed pulse width set to 5 clock cycles = 5* 50ns = 250 ns -- Fixed pulse width set to 5 clock cycles = 5* 50ns = 250 ns
g_pwidth : natural range 2 to 40 := 5; g_pwidth : natural range 2 to 40 := 5;
g_temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0); g_temp_decre_step : t_temp_decre_step :=
(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
--Scaled temperature rise resulting from single pulse. --Scaled temperature rise resulting from single pulse.
g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"01388";--5000 g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"01388"; --5000
-- Scaled maximum temperature ceiling before pulse inhibition is necessary to lower temperature -- Scaled maximum temperature ceiling before pulse inhibition
-- is necessary to lower temperature
g_max_temp :in unsigned (39 downto 0) := x"02540BE400" --10^10 g_max_temp :in unsigned (39 downto 0) := x"02540BE400" --10^10
); );
port port
( (
...@@ -72,18 +89,23 @@ entity conv_dyn_burst_ctrl is ...@@ -72,18 +89,23 @@ entity conv_dyn_burst_ctrl is
-- Enable input, high frequency repetition is enabled when '1' -- Enable input, high frequency repetition is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
-- Input pulse -- Asynchronous input pulse with rising and falling edges
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
--Dynamically controlled ouput pulse train. pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
-- Dynamic,temperature controlled ouput pulse train.
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives -- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase -- within a burst rejection phase
burst_err_p_o : out std_logic burst_err_p_o : out std_logic
); );
end entity conv_dyn_burst_ctrl; end entity conv_dyn_burst_ctrl;
-----------------------------------------------------------------------------------------
-- ARCHITECTURE
-----------------------------------------------------------------------------------------
architecture behav of conv_dyn_burst_ctrl is architecture behav of conv_dyn_burst_ctrl is
--type t_temp_decre_step is array (0 to 5) of integer; --type t_temp_decre_step is array (0 to 5) of integer;
...@@ -94,24 +116,6 @@ entity conv_dyn_burst_ctrl is ...@@ -94,24 +116,6 @@ entity conv_dyn_burst_ctrl is
PULSE_REJECT PULSE_REJECT
); );
--============================================================================
-- Function and procedure declarations: Function used if/when mode is extended to work for 1.2us pulse
--============================================================================
function f_th_array_lgth (pwidth : natural) return natural is
begin
if pwidth = 5 then --250ns wide pulses
return 6;
else
return 15; --1.2us wide pulses
end if;
end function f_th_array_lgth;
--============================================================================
-- Signal declarations
--============================================================================
--The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s, 36.66s and continuous" --The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s, 36.66s and continuous"
--for pulsing for frequencies 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively. --for pulsing for frequencies 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively.
--signal temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82); --signal temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82);
...@@ -119,51 +123,23 @@ entity conv_dyn_burst_ctrl is ...@@ -119,51 +123,23 @@ entity conv_dyn_burst_ctrl is
signal burst_ctrl_rst : std_logic; signal burst_ctrl_rst : std_logic;
signal pulse_train_in : std_logic; signal pulse_train_in : std_logic;
signal temp_rise : unsigned (39 downto 0) ; signal temp_rise : unsigned (39 downto 0) ;
signal test : integer ;
signal temp_fall : unsigned (39 downto 0) ;
signal single_cycle_cnt : integer; signal single_cycle_cnt : integer;
signal n_cycle_cnt : integer; signal n_cycle_cnt : integer range 0 to g_temp_decre_step'LENGTH;
signal pulse_train_in_d0 : std_logic; signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic; signal pulse_train_in_r_edge_p : std_logic;
signal pulse_train_in_f_edge_p : std_logic; signal pulse_train_in_f_edge_p : std_logic;
signal thermal_array_lgth :natural := 6;
signal state : t_state; signal state : t_state;
signal nxt_state : t_state; signal nxt_state : t_state;
constant thermal_res : natural := g_pwidth; -- thermal resolution in clock cycles constant thermal_res : natural := g_pwidth; -- thermal resolution in clock cycles
constant thermal_array_lgth :natural := f_th_array_lgth (g_pwidth);
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process (burst_ctrl_rst, pulse_burst_i)
begin begin
if (burst_ctrl_rst = '1') then
if falling_edge(pulse_burst_i) then -- wait for pulse to finish before cutoff
pulse_train_in <= '0';
end if;
elsif (en_i = '1') then
pulse_train_in <= pulse_burst_i; --re-activate output only if input line is off
end if;
end process p_pulse_redge;
thermal_array_lgth <= 6 when g_pwidth = 5 else 15;
pulse_burst_o <= pulse_train_in; --copy controlled input burst to output pulse_train_in <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
pulse_burst_o <= pulse_train_in;
--Synchronize the trigger in clk_i domain
p_pulse_redge_detect : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_train_in_d0 <= '0';
pulse_train_in_r_edge_p <= '0';
elsif (en_i='1') then
pulse_train_in_d0 <= pulse_burst_i;
pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
pulse_train_in_f_edge_p <= (not pulse_burst_i) and pulse_train_in_d0;
end if;
end if;
end process p_pulse_redge_detect;
--Process to count in n clk cycles steps --Process to count in n clk cycles steps
p_n_cycle_cnt : process(clk_i) p_n_cycle_cnt : process(clk_i)
...@@ -172,13 +148,13 @@ entity conv_dyn_burst_ctrl is ...@@ -172,13 +148,13 @@ entity conv_dyn_burst_ctrl is
if rst_n_i = '0' then if rst_n_i = '0' then
single_cycle_cnt <= 1; single_cycle_cnt <= 1;
n_cycle_cnt <= 1; n_cycle_cnt <= 1;
elsif (en_i = '1') then else
--reset counters in the event of a new pulse only when pulse rejection is not activ --reset counters in the event of a new pulse only when pulse rejection is not activ
if pulse_train_in_r_edge_p = '1' and burst_ctrl_rst = '0' then if (pulse_r_edge_p_i = '1' or pulse_f_edge_p_i = '1') and burst_ctrl_rst = '0' then
single_cycle_cnt <= 1; single_cycle_cnt <= 1;
n_cycle_cnt <= 1; n_cycle_cnt <= 1;
--When no pulse is being repeated, wither because pulse is off or because it is being rejected --When no pulse is being repeated, whether because pulse is off or because it is being rejected
elsif pulse_train_in = '0' then else
single_cycle_cnt <= single_cycle_cnt + 1; --count clk cycles single_cycle_cnt <= single_cycle_cnt + 1; --count clk cycles
if single_cycle_cnt = thermal_res then if single_cycle_cnt = thermal_res then
if n_cycle_cnt < thermal_array_lgth then if n_cycle_cnt < thermal_array_lgth then
...@@ -191,8 +167,14 @@ entity conv_dyn_burst_ctrl is ...@@ -191,8 +167,14 @@ entity conv_dyn_burst_ctrl is
end if; end if;
end process p_n_cycle_cnt; end process p_n_cycle_cnt;
-----------------------------------------------------------------------------------------
-- Finite State Machine FSM
-- Finite State Machine to control pulse repetition as a function of rising board temperature.
-- The FSM uses a temp_rise counter
-----------------------------------------------------------------------------------------
-- Process to implement FSM transitions -- Process to trigger state transitions
----------------------------------------
p_fsm_transitions: process(clk_i) p_fsm_transitions: process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -204,21 +186,21 @@ entity conv_dyn_burst_ctrl is ...@@ -204,21 +186,21 @@ entity conv_dyn_burst_ctrl is
end if; end if;
end process; end process;
-- FInite State Machine to control pulse repetition as a function of rising board temperature.
-- The FSM uses a temp_rise counter
p_thermal_fsm_states : process (state, pulse_train_in_r_edge_p, pulse_train_in_f_edge_p, temp_rise, n_cycle_cnt ) -- Process to define FSM states
--------------------------------
p_thermal_fsm_states : process (state, pulse_r_edge_p_i, pulse_f_edge_p_i, temp_rise, n_cycle_cnt )
begin begin
case state is case state is
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- The FSM is IDLE, when the board is completely "cool", temp_rise =0, and no -- The FSM is IDLE, when the board is completely "cool", temp_rise =0,
-- new pulses arrive after 1.75us from the last one -- and no new pulses arrive after 1.75us from the last one
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
when IDLE => when IDLE =>
if pulse_train_in_r_edge_p = '1' then if pulse_r_edge_p_i = '1' then
if temp_rise >= 0 and temp_rise <= g_max_temp then if temp_rise >= 0 and temp_rise < g_max_temp then
nxt_state <= PULSE_REPEAT; nxt_state <= PULSE_REPEAT;
else else
nxt_state <= PULSE_REJECT; nxt_state <= PULSE_REJECT;
...@@ -227,15 +209,17 @@ entity conv_dyn_burst_ctrl is ...@@ -227,15 +209,17 @@ entity conv_dyn_burst_ctrl is
end if; end if;
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- PULSE_REPEAT pulses are repeated as long as the temperature is below maximum g_max_temp. -- PULSE_REPEAT pulses are repeated as long as the temperature is below
-- While the temperature counter temp_rise is above 0, the time between 2 pulses is used to decrement it. -- maximum g_max_temp.
-- While the temperature counter temp_rise is above 0, the time between
-- 2 pulses is used to decrement it.
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
when PULSE_REPEAT => when PULSE_REPEAT =>
if temp_rise >= 0 and temp_rise <= g_max_temp then if temp_rise <= g_max_temp then
if pulse_train_in_r_edge_p = '1' then if pulse_r_edge_p_i = '1' then
nxt_state <= PULSE_REPEAT; nxt_state <= PULSE_REPEAT;
elsif temp_rise = 0 and n_cycle_cnt = 6 then--and temp_rise <= g_max_temp then elsif temp_rise = 0 and n_cycle_cnt = thermal_array_lgth then
nxt_state <= IDLE; nxt_state <= IDLE;
end if; end if;
else else
...@@ -243,13 +227,14 @@ entity conv_dyn_burst_ctrl is ...@@ -243,13 +227,14 @@ entity conv_dyn_burst_ctrl is
end if; end if;
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- PULSE_REJECT applies when a new pulse causes temperature to exceed maximum value -- PULSE_REJECT applies when a new pulse causes temperature to exceed
--i.e. temp_rise >= g_max_temp. -- maximum value
-- i.e. temp_rise >= g_max_temp.
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
when PULSE_REJECT => when PULSE_REJECT =>
if temp_rise <= g_max_temp then if temp_rise <= g_max_temp then
if pulse_train_in_f_edge_p ='1' then if pulse_f_edge_p_i ='1' then
nxt_state <= PULSE_REPEAT; nxt_state <= PULSE_REPEAT;
end if; end if;
else else
...@@ -260,9 +245,11 @@ entity conv_dyn_burst_ctrl is ...@@ -260,9 +245,11 @@ entity conv_dyn_burst_ctrl is
end process p_thermal_fsm_states; end process p_thermal_fsm_states;
p_thermal_fsm_outputs : process (clk_i)
-- Process to define FSM outputs
--------------------------------
p_thermal_fsm_outputs : process (state,pulse_r_edge_p_i, pulse_f_edge_p_i, single_cycle_cnt, n_cycle_cnt)
begin begin
if rising_edge(clk_i) then
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- The FSM is IDLE, when the board is completely "cool", temp_rise =0, and no -- The FSM is IDLE, when the board is completely "cool", temp_rise =0, and no
...@@ -285,23 +272,18 @@ entity conv_dyn_burst_ctrl is ...@@ -285,23 +272,18 @@ entity conv_dyn_burst_ctrl is
when PULSE_REPEAT => when PULSE_REPEAT =>
burst_ctrl_rst <= '0'; burst_ctrl_rst <= '0';
if temp_rise >= 0 and temp_rise <= g_max_temp then burst_err_p_o <= '0';
if pulse_train_in_f_edge_p = '1' then
if pulse_f_edge_p_i = '1' then
temp_rise <= temp_rise + g_1_pulse_temp_rise; temp_rise <= temp_rise + g_1_pulse_temp_rise;
elsif temp_rise /=0 and pulse_train_in_r_edge_p /= '1'then else
if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40); temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
else else
temp_rise <= (others => '0'); temp_rise <= (others => '0');
end if; end if;
end if; end if;
else
burst_ctrl_rst <= '1';
burst_err_p_o <= '0';
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
end if;
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
-- PULSE_REJECT applies when a new pulse causes temperature to exceed maximum value -- PULSE_REJECT applies when a new pulse causes temperature to exceed maximum value
...@@ -309,16 +291,11 @@ entity conv_dyn_burst_ctrl is ...@@ -309,16 +291,11 @@ entity conv_dyn_burst_ctrl is
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
when PULSE_REJECT => when PULSE_REJECT =>
burst_ctrl_rst <= '1'; burst_ctrl_rst <= '1';
burst_err_p_o <= '0'; burst_err_p_o <= pulse_r_edge_p_i;
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
temp_rise <= temp_rise - g_temp_decre_step(n_cycle_cnt-1); temp_rise <= temp_rise - g_temp_decre_step(n_cycle_cnt-1);
end case; end case;
end if;
end process p_thermal_fsm_outputs; end process p_thermal_fsm_outputs;
......
modules/conv_pulse_gen.vhd
View file @ eb610e84
...@@ -60,6 +60,7 @@ ...@@ -60,6 +60,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_gen is entity conv_pulse_gen is
generic generic
...@@ -102,7 +103,10 @@ entity conv_pulse_gen is ...@@ -102,7 +103,10 @@ entity conv_pulse_gen is
-- latency: -- latency:
-- glitch filter disabled: none -- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
); );
end entity conv_pulse_gen; end entity conv_pulse_gen;
...@@ -166,15 +170,18 @@ architecture behav of conv_pulse_gen is ...@@ -166,15 +170,18 @@ architecture behav of conv_pulse_gen is
signal pulse_gf_off_d1 : std_logic; signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic; signal pulse_gf_off_d2 : std_logic;
signal gen_edge_gf_off_n : std_logic;
signal trig_gf_on : std_logic; signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic; signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic; signal trig_gf_on_r_edge_p : std_logic;
signal trig_gf_on_f_edge_p : std_logic;
-- Pulse output signals -- Pulse output signals
signal pulse_gf_on : std_logic; signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic; signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic; signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic; signal pulse_gf_off_r_edge_p : std_logic;
signal pulse_gf_off_f_edge_p : std_logic;
-- Pulse length counter -- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0); signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
...@@ -215,22 +222,38 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate ...@@ -215,22 +222,38 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
end process p_pulse_gf_off; end process p_pulse_gf_off;
-- and synchronize the trigger in clk_i domain -- and synchronize the trigger in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is -- p_sync_pulse_gf_off: process (clk_i) is
begin -- begin
if rising_edge(clk_i) then -- if rising_edge(clk_i) then
if (rst_n_i = '0') then -- if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0'; -- pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0'; -- pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0'; -- pulse_gf_off_d2 <= '0';
pulse_gf_off_r_edge_p <= '0'; -- pulse_gf_off_r_edge_p <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then -- elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off; -- pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0; -- pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1; -- pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2); -- pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
end if; -- end if;
end if; -- end if;
end process p_sync_pulse_gf_off; -- end process p_sync_pulse_gf_off;
gen_edge_gf_off_n <= rst_n_i or en_i or gf_en_n_i;
-- and synchronize the trigger in clk_i domain using sync_ffs general core
cmp_gc_sync_ffs : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i, -- clock from the destination clock domain
rst_n_i => gen_edge_gf_off_n, -- reset is acomibnation of rst_n_i,
-- en_i and gf_en_n_i
data_i => pulse_gf_off, -- async input
npulse_o => pulse_gf_off_f_edge_p,-- negative edge detect output
ppulse_o => pulse_gf_off_r_edge_p-- positive edge detect output
);
-- Trigger signal with glitch filter ON is input signal -- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i; trig_gf_on <= trig_a_i;
...@@ -245,10 +268,13 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate ...@@ -245,10 +268,13 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
else else
trig_gf_on_d0 <= trig_gf_on; trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0); trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
trig_gf_on_f_edge_p <= (not trig_gf_on) and trig_gf_on_d0;
end if; end if;
end if; end if;
end process p_trig_gf_on; end process p_trig_gf_on;
pulse_r_edge_p_o <= pulse_gf_off_r_edge_p when gf_en_n_i = '1' else trig_gf_on_r_edge_p;
pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f_edge_p;
--============================================================================ --============================================================================
-- Pulse width adjustment logic -- Pulse width adjustment logic
--============================================================================ --============================================================================
......
top/conv_common_gw.vhd
View file @ eb610e84
...@@ -46,7 +46,6 @@ ...@@ -46,7 +46,6 @@
--Denia Bouhired Added support for one-wire thermometer register read out --Denia Bouhired Added support for one-wire thermometer register read out
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs -- 2016-12-20 Denia Bouhired Modified port list of conv_regs
-- 2017-01-25 Denia Bouhired Added pulse_width_sel and burst_en_n_i (Disables hi-freq bursts for all board versions)
--============================================================================== --==============================================================================
-- TODO: - -- TODO: -
--============================================================================== --==============================================================================
...@@ -320,8 +319,13 @@ architecture arch of conv_common_gw is ...@@ -320,8 +319,13 @@ architecture arch of conv_common_gw is
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0); signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0); signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0); signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_en_n : std_logic;
signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh_burst : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_sh_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg_burst : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_lg_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
...@@ -480,7 +484,7 @@ begin ...@@ -480,7 +484,7 @@ begin
generic map generic map
( (
-- Reset time: 50ns * 2 * (10**6) = 100 ms -- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6) g_reset_time => 2*(10**4)
) )
port map port map
( (
...@@ -520,12 +524,14 @@ begin ...@@ -520,12 +524,14 @@ begin
ttl_oen <= '0'; ttl_oen <= '0';
invttl_oen <= '0'; invttl_oen <= '0';
rear_oen <= '0'; rear_oen <= '0';
burst_en_n <= '0';
else else
global_oen <= '1'; global_oen <= '1';
if global_oen = '1' then if global_oen = '1' then
ttl_oen <= '1'; ttl_oen <= '1';
invttl_oen <= '1'; invttl_oen <= '1';
rear_oen <= '1'; rear_oen <= '1';
burst_en_n <= burst_en_n_i;
end if; end if;
end if; end if;
end if; end if;
...@@ -731,7 +737,9 @@ end generate gen_pulse_cnt; ...@@ -731,7 +737,9 @@ end generate gen_pulse_cnt;
pulse_err_p_o => pulse_outp_err_lg (i), pulse_err_p_o => pulse_outp_err_lg (i),
pulse_o => pulse_outp_lg(i) pulse_o => pulse_outp_lg(i),
pulse_r_edge_p_o => pulse_r_edge_lg_p(i),
pulse_f_edge_p_o => pulse_f_edge_lg_p(i)
); );
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel -- Instantiate burst control block for the channel
...@@ -749,6 +757,8 @@ end generate gen_pulse_cnt; ...@@ -749,6 +757,8 @@ end generate gen_pulse_cnt;
rst_n_i => rst_20_n, rst_n_i => rst_20_n,
en_i => '1', en_i => '1',
pulse_burst_i => pulse_outp_lg(i), pulse_burst_i => pulse_outp_lg(i),
pulse_r_edge_p_i => pulse_r_edge_lg_p(i),
pulse_f_edge_p_i => pulse_f_edge_lg_p(i),
pulse_burst_o => pulse_outp_lg_burst(i), pulse_burst_o => pulse_outp_lg_burst(i),
burst_err_p_o => burst_outp_err_lg (i) burst_err_p_o => burst_outp_err_lg (i)
...@@ -780,7 +790,10 @@ end generate gen_pulse_cnt; ...@@ -780,7 +790,10 @@ end generate gen_pulse_cnt;
pulse_err_p_o => pulse_outp_err_sh (i), pulse_err_p_o => pulse_outp_err_sh (i),
pulse_o => pulse_outp_sh(i) pulse_o => pulse_outp_sh(i),
pulse_r_edge_p_o => pulse_r_edge_sh_p(i) ,
pulse_f_edge_p_o => pulse_f_edge_sh_p(i)
); );
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel -- Instantiate burst control block for the channel
...@@ -798,6 +811,8 @@ end generate gen_pulse_cnt; ...@@ -798,6 +811,8 @@ end generate gen_pulse_cnt;
rst_n_i => rst_20_n, rst_n_i => rst_20_n,
en_i => '1', en_i => '1',
pulse_burst_i => pulse_outp_sh(i), pulse_burst_i => pulse_outp_sh(i),
pulse_r_edge_p_i => pulse_r_edge_sh_p(i),
pulse_f_edge_p_i => pulse_f_edge_sh_p(i),
pulse_burst_o => pulse_outp_sh_burst(i), pulse_burst_o => pulse_outp_sh_burst(i),
burst_err_p_o => burst_outp_err_sh (i) burst_err_p_o => burst_outp_err_sh (i)
); );
...@@ -805,29 +820,27 @@ end generate gen_pulse_cnt; ...@@ -805,29 +820,27 @@ end generate gen_pulse_cnt;
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
--Select output depending on mode of operation. --Select output depending on mode of operation.
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
p_output_sel : process (clk_20_i) is -- p_output_sel : process (burst_en_n, pulse_width_sel_n_i)
begin -- begin
if rising_edge(clk_20_i) then -- if burst_en_n = '1' then
--if (rst_20_n = '0') then -- pulse_outp(i) <= pulse_outp_cont(i);
-- pulse_outp(i) <= '0'; -- pmisse_p(i) <= pulse_outp_err_cont(i);
--else -- else
if burst_en_n_i = '1' then -- if pulse_width_sel_n_i='1' then
pulse_outp(i) <= pulse_outp_cont(i); -- pulse_outp(i) <= pulse_outp_lg_burst(i);
pmisse_p(i) <= pulse_outp_err_cont(i); -- pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i);
elsif pulse_width_sel_n_i='1' then -- else
pulse_outp(i) <= pulse_outp_lg_burst(i); -- pulse_outp(i) <= pulse_outp_sh_burst(i);
pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i); -- pmisse_p(i) <= pulse_outp_err_sh(i) or burst_outp_err_sh(i);
else -- end if;
pulse_outp(i) <= pulse_outp_sh_burst(i); -- end if;
pmisse_p(i) <= pulse_outp_err_sh(i) or burst_outp_err_sh(i); -- end process p_output_sel;
end if;
--end if;
end if; pulse_outp(i) <= (pulse_outp_lg_burst(i) and pulse_width_sel_n_i) or
end process p_output_sel; (pulse_outp_sh_burst(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i) ;
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
-- Process to flash pulse LED when a pulse is output -- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms -- LED flash length: 26 ms
......
top/conv_common_gw_pkg.vhd
View file @ eb610e84
...@@ -293,7 +293,9 @@ package conv_common_gw_pkg is ...@@ -293,7 +293,9 @@ package conv_common_gw_pkg is
-- latency: -- latency:
-- glitch filter disabled: none -- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
); );
end component conv_pulse_gen; end component conv_pulse_gen;
...@@ -324,6 +326,8 @@ package conv_common_gw_pkg is ...@@ -324,6 +326,8 @@ package conv_common_gw_pkg is
-- Enable input, pulse generation is enabled when '1' -- Enable input, pulse generation is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
......
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