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changes to conv common gateware manual for new release--unfinished

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doc/cern-title.tex
View file @ a7f5275f
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill August 29, 2014
\hfill 17 February 2017
\vspace*{3cm}
......@@ -24,7 +24,9 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\noindent {Last modified by \textit{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}\\
\noindent \rule{\textwidth}{.05cm}
......
doc/conv-common-gw.tex
View file @ a7f5275f
......@@ -357,8 +357,14 @@ Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed through a rising edge detector. When
a rising edge occurs on the pulse, the counter is incremented by one and stored
to the channel pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs})
register.
to the channel pulse counter register. There are two counters implemented separately for TTL
and BLO outputs of each channel (CHxTTLPCR and CHxBLOPCR -- see Appendix~\ref{app:conv-regs}).
Since the counters are incremented after the OR gate, the \textit{line\_front\_i} and \textit{line\_
rear\_i} are ANDed with the synched rising edge of the input line to determine whether the input
is a ttl or a blo signal. The corresponding counters are incremented accordingly. Figure~\ref{
fig:pulse-cnt} presents the implementation for the TTL case only, the same is duplicated for the
blocking counter.
The pulse counter register can be written via the \textit{conv\_regs} component as a
result of an I$^2$C write access to the register's address.
......@@ -495,7 +501,15 @@ The FSM waits in each state indefinitely for a value to be input.
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse generator}
\subsection{Pulse generation and dynamic burst control}
For hardware v4 of the CONV-TTL-BLO in particular (CONV-TTL-RS485 boards outputs are not sensitive to repetition frequency), release 4 of the gateware includes a \textit{burst mode} capability. Pulses output from the (\textit{conv\_pulse\_gen}) block, Sec~\ref{subsec:pulse-gen}, are fed onto to the \textit{conv\_dyn\_burst\_ctrl}, Sec~\ref{subsec:burst-ctrl}, where frequencies are limited over time and not on a pulse by pulse basis.
Moreover, v4 boards, give the possibility to select pulse width at the output via a \textit{general-purpose switch}. In addition to that, and for backwards compatibility with v3 boards and earlier, a fixed width, fixed frequency output is also available on the output for legacy boards\footnotemark.\footnotetext{These boards cannot handle high frequencies purely because of their hardware design and in that case \textit{burst mode} is disabled.}
Figure~\ref{fig:pulse-out-sel} shows how the output is selected depending on whether \textit{burst\_en\_n\_i} is activated or not, and also on which pulse width is selected (options are for \textit{SHORT} and \textit{LONG} pulses).
\subsubsection{Pulse generator}
\label{subsec:pulse-gen}
%------------------------------------------------------------------------------
......@@ -521,19 +535,51 @@ In this latter case, a finite-state machine (FSM) handles pulse generation and r
Its general operation is shown in Figure~\ref{fig:pulse-gen-operation}.
The operation of the pulse generator depends on whether the glitch filter is enabled.
If this is enabled, then the pulse is synchronized externally to the \textit{conv\_pulse\_gen}
block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the trigger
input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized and the
FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM resets
block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the
trigger
input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized
and the
FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM
resets
the input flip-flop and goes into the rejection state.
If any pulses arrive either during the generation state, or the rejection state, the error output
is set high for one clock cycle.
is set high for one clock cycle. This type of error is identified as a \textit{FLIM\_ERR\_p},
because they are to do with the maximum allowed frequency being reached.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
\end{figure}
\subsubsection{Dynamic burst controller}
\label{subsec:burst-ctrl}
The dynamic burst control block emulates temperature rise when new pulses arrive, when the
temperature counter reaches a pre-set maximum value (corresponding to maximum temperature), the
burst controller starts missing
pulses. This means that the board needs to \textit{cool off} between pulses and therefore
implements rejection only as long as the temperature is above the maximum. As soon as recovery is
achieved (temperature is again below maximum) the board starts repeating again.
The time at which the rejection starts depends on the frequency of the pulses coming out of the
\textit{Pulse Generator} block. For high frequencies, temperature will rise quickly and pulses
are rejected earlier. The lower the frequency the longer are repetition times.
The information relating repetition frequency and repetition times is embedded inside the FPGA and is generated in pre-processing and fed as a generic to the entity. The values used for a given thermal model is an array of constant values input as the \textit{g\_temp\_decre\_step} generic.
They differ for the SHORT and LONG pulse implementations. Appendix~\ref{app:} shows how these values can be generated in pre-processing.
In terms of gateware implementation, the \textit{conv\_dyn\_burst\_ctrl}, module uses a finite
state machine (FSM) to handle transitions between pulse repetition and pulse rejection depending
on the \textit{temp\_rise} counter value.
The FSM is triggered by pulse signals \textit{pulse\_r\_edge\_p\_i} and \textit{pulse\_f\_edge\_p\_i}
that had been generated as a result of synchronisation in the \textit{Pulse Generator} block. The
FSM outputs a \textit{burst\_ctrl\_rst} signal as a select signal to a multiplexer. The block's output replicates the input or clears it depending on the status of the \textit{burst\_ctrl\_rst} signal.
An pulse is generated every time a pulse is missed. This is the \textit{frequency watchdog error}, \textit{FWDG\_ERR\_p}, which signifies that the board has started to miss pulses
%------------------------------------------------------------------------------
\subsection{Pulse LED control}
\label{subsec:pulse-led}
......@@ -541,7 +587,7 @@ is set high for one clock cycle.
A rising edge on the \textit{pulse\_o} signal from the \textit{conv\_pulse\_gen}
block generates a 26-ms active-high pulse signal on the \textit{led\_pulse\_o} port of
\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output.
\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output. The same logic is used to drive LEDs on the inverting channels.
%==============================================================================
% SEC: Memory-mapped peripherals
......@@ -663,21 +709,28 @@ The \textit{xwb\_xil\_multiboot} module from the \textit{general-cores} library~
is used to provide MultiBoot functionality via I$^2$C. To find out more about the
module and how to use it, consult its documentation under the \textit{general-cores/doc/} folder.
%==============================================================================
\subsection{One-wire master}
%%==============================================================================
\subsection{One-wire temperature}
\label{subsec:onewire}
%==============================================================================
Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
which can be used for monitoring the temperature of, and obtaining a unique
identifier for the board.
The one-wire master module provides two registers for software control of the module.
Note that the FPGA does not control the one-wire thermometer lines in any way.
Accessing the thermometer is done through software only.
More details about how to access the one-wire master module can be found in its
documentation~\cite{onewire-core}.
%%==============================================================================
The \textit{conv\_common\_gw} used a one-wire interface module (\textit{gc\_ds182x\_interface}) to the one-wire ds182x thermometer chip present on the board.
The module requires the thermometer input \textit{thermometer\_b}, directly from the board plus a pps (pulse-per-second) signal (generated by \textit{wf\_decr\_counter} component). This interface outputs the chip unique ID as a 64-bit value, and the board temperature as a 16-bit value. These 2 values result in 3 memory mapped registers, 2, 32-bit registers for the chip ID, and 1 for the temperature.
.
%%==============================================================================
%\subsection{One-wire master}
%\label{subsec:onewire}
%%==============================================================================
%
%Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
%which can be used for monitoring the temperature of, and obtaining a unique
%identifier for the board.
%
%The one-wire master module provides two registers for software control of the module.
%Note that the FPGA does not control the one-wire thermometer lines in any way.
%Accessing the thermometer is done through software only.
%
%More details about how to access the one-wire master module can be found in its
%documentation~\cite{onewire-core}.
%==============================================================================
% Appendices
......@@ -711,7 +764,7 @@ The following sections list the memory map of each peripheral.
\hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x11f & MultiBoot module \\
One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
%One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
\hline
\end{tabular}
......@@ -731,34 +784,34 @@ The following sections list the memory map of each peripheral.
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x200
\vspace*{11pt}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%\subsection{Thermometer module}
%\label{app:memmap-thermo}
%
%\indent Base address: 0x200
%
%\vspace*{11pt}
%
%\centerline
%{
%\rowcolors{2}{white}{gray!25}
%\begin{tabular}{l l l p{.5\textwidth}}
%\hline
%\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
%\hline
%0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
%0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
%\hline
%\end{tabular}
%}
%
%\vspace*{11pt}
%
%For details on the bits of the thermometer module access registers, see the
%OneWire Master module's documentation~\cite{onewire-core}.
%
%Note that the OWCDR should be set accordingly for proper functioning of the
%one-wire timings. The value for the current version of the gateware is
%\verb-OWCDR = 0x00130063-.
%==============================================================================
% APP: Changing the code for more than six pulse repetition channels
......
doc/conv-regs.tex
View file @ a7f5275f
......@@ -17,54 +17,69 @@ Base address: 0x000
\endhead
\hline
\endfoot
0x0 & \textit{g\_board\_id} & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x40 & 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x44 & 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x48 & 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
0x4c & 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
0x50 & 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
0x54 & 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
0x58 & 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
0x5c & 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
0x60 & 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
0x64 & 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
0x68 & 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
0x6c & 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
0x70 & 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
0x74 & 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
0x78 & 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
0x7c & 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0x88 & (2) & LSR & Line Status Register\\
0x8c & 0x00000000 & OSWR & Other Switches Register\\
0x0& 0x54424c4f & BIDR & Board ID Register\\
0x4& Note(1)& SR & Status Register\\
0x8& 0x00000000 & ERR & Error Register\\
0xc& 0x00000000 & CR & Control Register\\
0x10& 0x00000000 & CH1TTLPCR & Channel 1 TTL Pulse Counter Register\\
0x14& 0x00000000 & CH2TTLPCR & Channel 2 TTL Pulse Counter Register\\
0x18& 0x00000000 & CH3TTLPCR & Channel 3 TTL Pulse Counter Register\\
0x1c& 0x00000000 & CH4TTLPCR & Channel 4 TTL Pulse Counter Register\\
0x20& 0x00000000 & CH5TTLPCR & Channel 5 TTL Pulse Counter Register\\
0x24& 0x00000000 & CH6TTLPCR & Channel 6 TTL Pulse Counter Register\\
0x28& 0x00000000 & CH1BLOPCR & Channel 1 BLO Pulse Counter Register\\
0x2c& 0x00000000 & CH2BLOPCR & Channel 2 BLO Pulse Counter Register\\
0x30& 0x00000000 & CH3BLOPCR & Channel 3 BLO Pulse Counter Register\\
0x34& 0x00000000 & CH4BLOPCR & Channel 4 BLO Pulse Counter Register\\
0x38& 0x00000000 & CH5BLOPCR & Channel 5 BLO Pulse Counter Register\\
0x3c& 0x00000000 & CH6BLOPCR & Channel 6 BLO Pulse Counter Register\\
0x40& 0x00000000 & TVLR & Time Value Low Register\\
0x44& 0x00000000 & TVHR & Time Value High Register\\
0x48& 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x4c& 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x50& 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x54& 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x58& 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x5c& 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x60& 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x64& 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
0x68& 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
0x6c& 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
0x70& 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
0x74& 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
0x78& 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
0x7c& 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
0x80& 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
0x84& 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
0x88& 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
0x8c& 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
0x90& 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
0x94& 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
0x98& 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x9c& 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0xa0& 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0xa4& Note(2) & LSR & Line Status Register\\
0xa8& 0x00000000 & OSWR & Other switch resistor\\
0xac& Unique ID & UIDLR & Thermometer ID Low register\\
0xb0& Unique ID & UIDHR & Thermometer ID High register\\
0xb4& 0x00000000 & TEMPR & Board Temperature Register\\
\hline
\end{longtable}
}
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\label{app:conv-regs-BIDR}
\vspace{11pt}
\noindent
......@@ -95,27 +110,30 @@ is plugged into the channel or not.
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: \textit{g\_board\_id}
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\label{app:conv-regs-SR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{6}{|c|}{\cellcolor{gray!25}PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{4}{|c|}{\cellcolor{gray!25}HWVERS[5:2]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\multicolumn{2}{|c|}{\cellcolor{gray!25}HWVERS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
......@@ -141,21 +159,21 @@ Leftmost nibble hex value is major release decimal value \\
SWITCHES
} [\emph{read-only}]: Status of on-board general-purpose switches
\\
1 -- switch is ON \\ 0 -- switch is OFF
Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\ SW2.1-- SR.SWITCHES[4] \\ SW2.4-- SR.SWITCHES[7] \\ 1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
} [\emph{read-only}]: RTM detection lines cite{rtm-det}
\\
1 -- line active \\ 0 -- line inactive
1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
HWVERS
} [\emph{read-only}]: Hardware version
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
PCB version - Hardwired on the board \\ Only meaningful for HW v4.0 and over \\ Earlier versions show 0. The register \\ uses 4 bits for the version number and\\ 2 bits for the execution.\\ e.g. \\ 0x010001 -- hw v4.1 \\ 0x010111 -- hw v5.3 \\ 0x00-- hw v3 and earlier
\end{small}
\item \begin{small}
{\bf
......@@ -164,6 +182,42 @@ WRPRES
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\end{itemize}
\subsubsection{ERR - Error Register}
\label{app:conv-regs-ERR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FWDG\_PMISSE[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}FLIM\_PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
......@@ -173,19 +227,21 @@ I2C\_ERR
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
FLIM\_PMISSE
} [\emph{read/write}]: Frequency error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
1 -- Input above maximum supported frequency \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
FWDG\_PMISSE
} [\emph{read/write}]: Frequency watchdog error
\\
1 -- Pulse over maximum pulse count for given frequency' \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\subsubsection{CR - Control Register}
\label{app:conv-regs-CR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -220,7 +276,7 @@ RST\_UNLOCK
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
......@@ -235,29 +291,28 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\subsubsection{CH1TTLPCR - Channel 1 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH1TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -265,16 +320,14 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\begin{itemize}
\item \begin{small}
{\bf
CH1PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
CH1TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\subsubsection{CH2TTLPCR - Channel 2 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH2TTLPCR}
\vspace{11pt}
\noindent
......@@ -282,19 +335,19 @@ CH1PCR
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -302,16 +355,46 @@ CH1PCR
\begin{itemize}
\item \begin{small}
{\bf
CH2PCR
} [\emph{read/write}]: Pulse counter value
CH2TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH3TTLPCR - Channel 3 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH3TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
CH3TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\subsubsection{CH4TTLPCR - Channel 4 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH4TTLPCR}
\vspace{11pt}
\noindent
......@@ -319,19 +402,19 @@ CH2PCR
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -339,16 +422,46 @@ CH2PCR
\begin{itemize}
\item \begin{small}
{\bf
CH3PCR
} [\emph{read/write}]: Pulse counter value
CH4TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH5TTLPCR - Channel 5 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH5TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
CH5TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\subsubsection{CH6TTLPCR - Channel 6 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH6TTLPCR}
\vspace{11pt}
\noindent
......@@ -356,19 +469,19 @@ CH3PCR
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -376,16 +489,45 @@ CH3PCR
\begin{itemize}
\item \begin{small}
{\bf
CH4PCR
} [\emph{read/write}]: Pulse counter value
CH6TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH1BLOPCR - Channel 1 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH1BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
CH1BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\subsubsection{CH2BLOPCR - Channel 2 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH2BLOPCR}
\vspace{11pt}
\noindent
......@@ -393,19 +535,19 @@ CH4PCR
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -413,16 +555,46 @@ CH4PCR
\begin{itemize}
\item \begin{small}
{\bf
CH5PCR
} [\emph{read/write}]: Pulse counter value
CH2BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH3BLOPCR - Channel 3 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH3BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
CH3BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\subsubsection{CH4BLOPCR - Channel 4 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH4BLOPCR}
\vspace{11pt}
\noindent
......@@ -430,19 +602,19 @@ CH5PCR
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -450,16 +622,80 @@ CH5PCR
\begin{itemize}
\item \begin{small}
{\bf
CH6PCR
} [\emph{read/write}]: Pulse counter value
CH4BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH5BLOPCR - Channel 5 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH5BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
CH5BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH6BLOPCR - Channel 6 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH6BLOPCR}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{TVLR - Time Value Low Register}
\label{app:conv-regs-TVLR}
\vspace{11pt}
\noindent
......@@ -492,13 +728,11 @@ TVLR
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\subsubsection{TVHR - Time Value High Register}
\label{app:conv-regs-TVHR}
\vspace{11pt}
\noindent
......@@ -531,14 +765,9 @@ TVHR
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\subsubsection{TBMR - Tag Buffer Meta Register}
\label{app:conv-regs-TBMR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -577,16 +806,9 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\subsubsection{TBCYR - Tag Buffer Cycles Register}
\label{app:conv-regs-TBCYR}
\vspace{11pt}
\noindent
......@@ -619,13 +841,11 @@ TBCYR
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\subsubsection{TBTLR - Tag Buffer TAI Low Register}
\label{app:conv-regs-TBTLR}
\vspace{11pt}
\noindent
......@@ -658,14 +878,10 @@ TBTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\pagebreak
\vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
\subsubsection{TBTHR - Tag Buffer TAI High Register}
\label{app:conv-regs-TBTHR}
\vspace{11pt}
\noindent
......@@ -698,14 +914,9 @@ TBTHR
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\subsubsection{TBCSR - Tag Buffer Control and Status Register}
\label{app:conv-regs-TBCSR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -758,14 +969,9 @@ CLR
\\
1 -- clear\\ 0 -- no effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSCYR -- Channel 1 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch1ltscyr}
\subsubsection{CH1LTSCYR - Channel 1 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH1LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -793,17 +999,14 @@ CLR
\item \begin{small}
{\bf
CH1LTSCYR
} [\emph{write-only}]: Cycles counter
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSTLR -- Channel 1 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch1ltstlr}
\subsubsection{CH1LTSTLR - Channel 1 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH1LTSTLR}
\vspace{11pt}
\noindent
......@@ -836,15 +1039,10 @@ CH1LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSTHR - Channel 1 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH1LTSTHR}
\pagebreak
\subsubsection{CH1LTSTHR -- Channel 1 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch1ltsthr}
\vspace{11pt}
\noindent
......@@ -884,14 +1082,9 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSCYR -- Channel 2 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch2ltscyr}
\subsubsection{CH2LTSCYR - Channel 2 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH2LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -919,18 +1112,13 @@ WRTAG
\item \begin{small}
{\bf
CH2LTSCYR
} [\emph{write-only}]: Cycles counter
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTLR -- Channel 2 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch2ltstlr}
\subsubsection{CH2LTSTLR - Channel 2 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH2LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -962,14 +1150,9 @@ CH2LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTHR -- Channel 2 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch2ltsthr}
\subsubsection{CH2LTSTHR - Channel 2 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH2LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1008,14 +1191,9 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSCYR -- Channel 3 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch3ltscyr}
\subsubsection{CH3LTSCYR - Channel 3 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH3LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1043,18 +1221,13 @@ WRTAG
\item \begin{small}
{\bf
CH3LTSCYR
} [\emph{write-only}]: Cycles counter
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSTLR -- Channel 3 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch3ltstlr}
\subsubsection{CH3LTSTLR - Channel 3 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH3LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1086,15 +1259,9 @@ CH3LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH3LTSTHR -- Channel 3 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch3ltsthr}
\subsubsection{CH3LTSTHR - Channel 3 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH3LTSTHR}
\vspace{11pt}
\noindent
......@@ -1134,33 +1301,28 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSCYR -- Channel 4 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch4ltscyr}
\subsubsection{CH4LTSCYR - Channel 4 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH4LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TAI[27:24]}\\
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH4LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[7:0]}\\
\hline
\end{tabular}
}
......@@ -1168,19 +1330,14 @@ WRTAG
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{write-only}]: Cycles counter
CH4LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTLR -- Channel 4 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch4ltstlr}
\subsubsection{CH4LTSTLR - Channel 4 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH4LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1212,14 +1369,9 @@ CH4LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTHR -- Channel 4 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch4ltsthr}
\subsubsection{CH4LTSTHR - Channel 4 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH4LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1258,14 +1410,9 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSCYR -- Channel 5 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch5ltscyr}
\subsubsection{CH5LTSCYR - Channel 5 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH5LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1293,18 +1440,13 @@ WRTAG
\item \begin{small}
{\bf
CH5LTSCYR
} [\emph{write-only}]: Cycles counter
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSTLR -- Channel 5 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch5ltstlr}
\subsubsection{CH5LTSTLR - Channel 5 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH5LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1336,15 +1478,9 @@ CH5LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH5LTSTHR -- Channel 5 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch5ltsthr}
\subsubsection{CH5LTSTHR - Channel 5 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH5LTSTHR}
\vspace{11pt}
\noindent
......@@ -1384,14 +1520,9 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSCYR -- Channel 6 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch6ltscyr}
\subsubsection{CH6LTSCYR - Channel 6 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH6LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1419,17 +1550,13 @@ WRTAG
\item \begin{small}
{\bf
CH6LTSCYR
} [\emph{write-only}]: Cycles counter
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTLR -- Channel 6 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch6ltstlr}
\subsubsection{CH6LTSTLR - Channel 6 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH6LTSTLR}
\vspace{11pt}
\noindent
......@@ -1462,14 +1589,9 @@ CH6LTSTLR
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTHR -- Channel 6 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch6ltsthr}
\subsubsection{CH6LTSTHR - Channel 6 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH6LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1508,12 +1630,8 @@ WRTAG
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\subsubsection{LSR - Line Status Register}
\label{app:conv-regs-lsr}
\vspace{11pt}
......@@ -1582,15 +1700,9 @@ REARFS
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{OSWR -- Other Switches Register}
\label{app:conv-regs-oswr}
\subsubsection{OSWR - Other Switch Register}
\label{app:conv-regs-OSWR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
......@@ -1622,7 +1734,107 @@ SWITCHES
\\
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\end{itemize}
\subsubsection{UIDLR - 32 LS bits of 1-wire thermometer ID}
\label{app:conv-regs-UIDLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
UIDLR
} [\emph{read-only}]: LS bits of 1-wire DS18B20U thermometer ID
\end{small}
\end{itemize}
\subsubsection{UIDHR - 32 MS bits of 1-wire thermometer ID}
\label{app:conv-regs-UIDHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
UIDHR
} [\emph{read-only}]: MS bits of 1-wire DS18B20U thermometer ID
\end{small}
\end{itemize}
\subsubsection{TEMPR - Temperature Resgister }
\label{app:conv-regs-TEMPR}
Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to ${}^{o}C$ as follows: Temp = register value / 16.0
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TEMPR
} [\emph{read-only}]: TEMP
\\
Current on-board temperature
\end{small}
\end{itemize}
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