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conv-common-gw
Commit 9b832b6a authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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wbgen2 generated files with new register names (no change to memory map

parent 0f499dc4
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modules/conv_regs.h
View file @ 9b832b6a
......@@ -2,17 +2,17 @@
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 02/06/17 15:05:15
* Author : auto-generated by wbgen2 from .\conv_regs.wb
* Created : 09/26/17 10:50:26
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS__\CONV_REGS_WB
#define __WBGEN2_REGDEFS__\CONV_REGS_WB
#include <inttypes.h>
......@@ -96,29 +96,29 @@
#define REG_CR_MPT_W(value) WBGEN2_GEN_WRITE(value, 2, 8)
#define REG_CR_MPT_R(reg) WBGEN2_GEN_READ(reg, 2, 8)
/* definitions for register: CH1TTLPCR */
/* definitions for register: CH1FPPCR */
/* definitions for register: CH2TTLPCR */
/* definitions for register: CH2FPPCR */
/* definitions for register: CH3TTLPCR */
/* definitions for register: CH3FPPCR */
/* definitions for register: CH4TTLPCR */
/* definitions for register: CH4FPPCR */
/* definitions for register: CH5TTLPCR */
/* definitions for register: CH5FPPCR */
/* definitions for register: CH6TTLPCR */
/* definitions for register: CH6FPPCR */
/* definitions for register: CH1BLOPCR */
/* definitions for register: CH1RPPCR */
/* definitions for register: CH2BLOPCR */
/* definitions for register: CH2RPPCR */
/* definitions for register: CH3BLOPCR */
/* definitions for register: CH3RPPCR */
/* definitions for register: CH4BLOPCR */
/* definitions for register: CH4RPPCR */
/* definitions for register: CH5BLOPCR */
/* definitions for register: CH5RPPCR */
/* definitions for register: CH6BLOPCR */
/* definitions for register: CH6RPPCR */
/* definitions for register: TVLR */
......@@ -299,96 +299,100 @@
/* definitions for register: UIDHR */
/* definitions for register: TEMPR */
/* [0x0]: REG BIDR */
#define REG_REG_BIDR 0x00000000
/* [0x4]: REG SR */
#define REG_REG_SR 0x00000004
/* [0x8]: REG ERR */
#define REG_REG_ERR 0x00000008
/* [0xc]: REG CR */
#define REG_REG_CR 0x0000000c
/* [0x10]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x00000010
/* [0x14]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000014
/* [0x18]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000018
/* [0x1c]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x0000001c
/* [0x20]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x00000020
/* [0x24]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000024
/* [0x28]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000028
/* [0x2c]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x0000002c
/* [0x30]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x00000030
/* [0x34]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000034
/* [0x38]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000038
/* [0x3c]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x0000003c
/* [0x40]: REG TVLR */
#define REG_REG_TVLR 0x00000040
/* [0x44]: REG TVHR */
#define REG_REG_TVHR 0x00000044
/* [0x48]: REG TBMR */
#define REG_REG_TBMR 0x00000048
/* [0x4c]: REG TBCYR */
#define REG_REG_TBCYR 0x0000004c
/* [0x50]: REG TBTLR */
#define REG_REG_TBTLR 0x00000050
/* [0x54]: REG TBTHR */
#define REG_REG_TBTHR 0x00000054
/* [0x58]: REG TBCSR */
#define REG_REG_TBCSR 0x00000058
/* [0x5c]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x0000005c
/* [0x60]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x00000060
/* [0x64]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000064
/* [0x68]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000068
/* [0x6c]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x0000006c
/* [0x70]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x00000070
/* [0x74]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000074
/* [0x78]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000078
/* [0x7c]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x0000007c
/* [0x80]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x00000080
/* [0x84]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000084
/* [0x88]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000088
/* [0x8c]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x0000008c
/* [0x90]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x00000090
/* [0x94]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000094
/* [0x98]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000098
/* [0x9c]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x0000009c
/* [0xa0]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x000000a0
/* [0xa4]: REG LSR */
#define REG_REG_LSR 0x000000a4
/* [0xa8]: REG OSWR */
#define REG_REG_OSWR 0x000000a8
/* [0xac]: REG UIDLR */
#define REG_REG_UIDLR 0x000000ac
/* [0xb0]: REG UIDHR */
#define REG_REG_UIDHR 0x000000b0
/* [0xb4]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b4
PACKED struct REG_WB {
/* [0x0]: REG BIDR */
uint32_t BIDR;
/* [0x4]: REG SR */
uint32_t SR;
/* [0x8]: REG ERR */
uint32_t ERR;
/* [0xc]: REG CR */
uint32_t CR;
/* [0x10]: REG CH1FPPCR */
uint32_t CH1FPPCR;
/* [0x14]: REG CH2FPPCR */
uint32_t CH2FPPCR;
/* [0x18]: REG CH3FPPCR */
uint32_t CH3FPPCR;
/* [0x1c]: REG CH4FPPCR */
uint32_t CH4FPPCR;
/* [0x20]: REG CH5FPPCR */
uint32_t CH5FPPCR;
/* [0x24]: REG CH6FPPCR */
uint32_t CH6FPPCR;
/* [0x28]: REG CH1RPPCR */
uint32_t CH1RPPCR;
/* [0x2c]: REG CH2RPPCR */
uint32_t CH2RPPCR;
/* [0x30]: REG CH3RPPCR */
uint32_t CH3RPPCR;
/* [0x34]: REG CH4RPPCR */
uint32_t CH4RPPCR;
/* [0x38]: REG CH5RPPCR */
uint32_t CH5RPPCR;
/* [0x3c]: REG CH6RPPCR */
uint32_t CH6RPPCR;
/* [0x40]: REG TVLR */
uint32_t TVLR;
/* [0x44]: REG TVHR */
uint32_t TVHR;
/* [0x48]: REG TBMR */
uint32_t TBMR;
/* [0x4c]: REG TBCYR */
uint32_t TBCYR;
/* [0x50]: REG TBTLR */
uint32_t TBTLR;
/* [0x54]: REG TBTHR */
uint32_t TBTHR;
/* [0x58]: REG TBCSR */
uint32_t TBCSR;
/* [0x5c]: REG CH1LTSCYR */
uint32_t CH1LTSCYR;
/* [0x60]: REG CH1LTSTLR */
uint32_t CH1LTSTLR;
/* [0x64]: REG CH1LTSTHR */
uint32_t CH1LTSTHR;
/* [0x68]: REG CH2LTSCYR */
uint32_t CH2LTSCYR;
/* [0x6c]: REG CH2LTSTLR */
uint32_t CH2LTSTLR;
/* [0x70]: REG CH2LTSTHR */
uint32_t CH2LTSTHR;
/* [0x74]: REG CH3LTSCYR */
uint32_t CH3LTSCYR;
/* [0x78]: REG CH3LTSTLR */
uint32_t CH3LTSTLR;
/* [0x7c]: REG CH3LTSTHR */
uint32_t CH3LTSTHR;
/* [0x80]: REG CH4LTSCYR */
uint32_t CH4LTSCYR;
/* [0x84]: REG CH4LTSTLR */
uint32_t CH4LTSTLR;
/* [0x88]: REG CH4LTSTHR */
uint32_t CH4LTSTHR;
/* [0x8c]: REG CH5LTSCYR */
uint32_t CH5LTSCYR;
/* [0x90]: REG CH5LTSTLR */
uint32_t CH5LTSTLR;
/* [0x94]: REG CH5LTSTHR */
uint32_t CH5LTSTHR;
/* [0x98]: REG CH6LTSCYR */
uint32_t CH6LTSCYR;
/* [0x9c]: REG CH6LTSTLR */
uint32_t CH6LTSTLR;
/* [0xa0]: REG CH6LTSTHR */
uint32_t CH6LTSTHR;
/* [0xa4]: REG LSR */
uint32_t LSR;
/* [0xa8]: REG OSWR */
uint32_t OSWR;
/* [0xac]: REG UIDLR */
uint32_t UIDLR;
/* [0xb0]: REG UIDHR */
uint32_t UIDHR;
/* [0xb4]: REG TEMPR */
uint32_t TEMPR;
};
#endif
modules/conv_regs.htm
View file @ 9b832b6a
......@@ -38,18 +38,18 @@
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">SR</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">ERR</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">CR</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">CH1TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">CH2TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">CH3TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">CH4TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">CH5TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">CH6TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">CH1BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">CH2BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">CH3BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">CH4BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">CH5BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">CH6BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">CH1FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">CH2FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">CH3FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">CH4FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">CH5FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">CH6FPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">CH1RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">CH2RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">CH3RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">CH4RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">CH5RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">CH6RPPCR</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">TVLR</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">TVHR</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">TBMR</a></span><br/>
......@@ -175,13 +175,13 @@ CR
REG
</td>
<td >
<A href="#CH1TTLPCR">CH1TTLPCR</a>
<A href="#CH1FPPCR">CH1FPPCR</a>
</td>
<td class="td_code">
reg_ch1ttlpcr
reg_ch1fppcr
</td>
<td class="td_code">
CH1TTLPCR
CH1FPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -192,13 +192,13 @@ CH1TTLPCR
REG
</td>
<td >
<A href="#CH2TTLPCR">CH2TTLPCR</a>
<A href="#CH2FPPCR">CH2FPPCR</a>
</td>
<td class="td_code">
reg_ch2ttlpcr
reg_ch2fppcr
</td>
<td class="td_code">
CH2TTLPCR
CH2FPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -209,13 +209,13 @@ CH2TTLPCR
REG
</td>
<td >
<A href="#CH3TTLPCR">CH3TTLPCR</a>
<A href="#CH3FPPCR">CH3FPPCR</a>
</td>
<td class="td_code">
reg_ch3ttlpcr
reg_ch3fppcr
</td>
<td class="td_code">
CH3TTLPCR
CH3FPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -226,13 +226,13 @@ CH3TTLPCR
REG
</td>
<td >
<A href="#CH4TTLPCR">CH4TTLPCR</a>
<A href="#CH4FPPCR">CH4FPPCR</a>
</td>
<td class="td_code">
reg_ch4ttlpcr
reg_ch4fppcr
</td>
<td class="td_code">
CH4TTLPCR
CH4FPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -243,13 +243,13 @@ CH4TTLPCR
REG
</td>
<td >
<A href="#CH5TTLPCR">CH5TTLPCR</a>
<A href="#CH5FPPCR">CH5FPPCR</a>
</td>
<td class="td_code">
reg_ch5ttlpcr
reg_ch5fppcr
</td>
<td class="td_code">
CH5TTLPCR
CH5FPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -260,13 +260,13 @@ CH5TTLPCR
REG
</td>
<td >
<A href="#CH6TTLPCR">CH6TTLPCR</a>
<A href="#CH6FPPCR">CH6FPPCR</a>
</td>
<td class="td_code">
reg_ch6ttlpcr
reg_ch6fppcr
</td>
<td class="td_code">
CH6TTLPCR
CH6FPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -277,13 +277,13 @@ CH6TTLPCR
REG
</td>
<td >
<A href="#CH1BLOPCR">CH1BLOPCR</a>
<A href="#CH1RPPCR">CH1RPPCR</a>
</td>
<td class="td_code">
reg_ch1blopcr
reg_ch1rppcr
</td>
<td class="td_code">
CH1BLOPCR
CH1RPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -294,13 +294,13 @@ CH1BLOPCR
REG
</td>
<td >
<A href="#CH2BLOPCR">CH2BLOPCR</a>
<A href="#CH2RPPCR">CH2RPPCR</a>
</td>
<td class="td_code">
reg_ch2blopcr
reg_ch2rppcr
</td>
<td class="td_code">
CH2BLOPCR
CH2RPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -311,13 +311,13 @@ CH2BLOPCR
REG
</td>
<td >
<A href="#CH3BLOPCR">CH3BLOPCR</a>
<A href="#CH3RPPCR">CH3RPPCR</a>
</td>
<td class="td_code">
reg_ch3blopcr
reg_ch3rppcr
</td>
<td class="td_code">
CH3BLOPCR
CH3RPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -328,13 +328,13 @@ CH3BLOPCR
REG
</td>
<td >
<A href="#CH4BLOPCR">CH4BLOPCR</a>
<A href="#CH4RPPCR">CH4RPPCR</a>
</td>
<td class="td_code">
reg_ch4blopcr
reg_ch4rppcr
</td>
<td class="td_code">
CH4BLOPCR
CH4RPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -345,13 +345,13 @@ CH4BLOPCR
REG
</td>
<td >
<A href="#CH5BLOPCR">CH5BLOPCR</a>
<A href="#CH5RPPCR">CH5RPPCR</a>
</td>
<td class="td_code">
reg_ch5blopcr
reg_ch5rppcr
</td>
<td class="td_code">
CH5BLOPCR
CH5RPPCR
</td>
</tr>
<tr class="tr_even">
......@@ -362,13 +362,13 @@ CH5BLOPCR
REG
</td>
<td >
<A href="#CH6BLOPCR">CH6BLOPCR</a>
<A href="#CH6RPPCR">CH6RPPCR</a>
</td>
<td class="td_code">
reg_ch6blopcr
reg_ch6rppcr
</td>
<td class="td_code">
CH6BLOPCR
CH6RPPCR
</td>
</tr>
<tr class="tr_odd">
......@@ -1474,7 +1474,7 @@ reg_cr_mpt_wr_o
</td>
<td class="td_pblock_right">
<b>CH1TTLPCR:</b>
<b>CH1FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1491,7 +1491,7 @@ reg_cr_mpt_wr_o
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_o[31:0]
reg_ch1fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1508,7 +1508,7 @@ reg_ch1ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_i[31:0]
reg_ch1fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1525,7 +1525,7 @@ reg_ch1ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_load_o
reg_ch1fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1559,7 +1559,7 @@ reg_ch1ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH2TTLPCR:</b>
<b>CH2FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1576,7 +1576,7 @@ reg_ch1ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch2ttlpcr_o[31:0]
reg_ch2fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1593,7 +1593,7 @@ reg_ch2ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch2ttlpcr_i[31:0]
reg_ch2fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1610,7 +1610,7 @@ reg_ch2ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch2ttlpcr_load_o
reg_ch2fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1644,7 +1644,7 @@ reg_ch2ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH3TTLPCR:</b>
<b>CH3FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1661,7 +1661,7 @@ reg_ch2ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch3ttlpcr_o[31:0]
reg_ch3fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1678,7 +1678,7 @@ reg_ch3ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch3ttlpcr_i[31:0]
reg_ch3fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1695,7 +1695,7 @@ reg_ch3ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch3ttlpcr_load_o
reg_ch3fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1729,7 +1729,7 @@ reg_ch3ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH4TTLPCR:</b>
<b>CH4FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1746,7 +1746,7 @@ reg_ch3ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch4ttlpcr_o[31:0]
reg_ch4fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1763,7 +1763,7 @@ reg_ch4ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch4ttlpcr_i[31:0]
reg_ch4fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1780,7 +1780,7 @@ reg_ch4ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch4ttlpcr_load_o
reg_ch4fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1814,7 +1814,7 @@ reg_ch4ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH5TTLPCR:</b>
<b>CH5FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1831,7 +1831,7 @@ reg_ch4ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch5ttlpcr_o[31:0]
reg_ch5fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1848,7 +1848,7 @@ reg_ch5ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch5ttlpcr_i[31:0]
reg_ch5fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1865,7 +1865,7 @@ reg_ch5ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch5ttlpcr_load_o
reg_ch5fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1899,7 +1899,7 @@ reg_ch5ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH6TTLPCR:</b>
<b>CH6FPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -1916,7 +1916,7 @@ reg_ch5ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch6ttlpcr_o[31:0]
reg_ch6fppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1933,7 +1933,7 @@ reg_ch6ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch6ttlpcr_i[31:0]
reg_ch6fppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1950,7 +1950,7 @@ reg_ch6ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch6ttlpcr_load_o
reg_ch6fppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1984,7 +1984,7 @@ reg_ch6ttlpcr_load_o
</td>
<td class="td_pblock_right">
<b>CH1BLOPCR:</b>
<b>CH1RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2001,7 +2001,7 @@ reg_ch6ttlpcr_load_o
</td>
<td class="td_pblock_right">
reg_ch1blopcr_o[31:0]
reg_ch1rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2018,7 +2018,7 @@ reg_ch1blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch1blopcr_i[31:0]
reg_ch1rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2035,7 +2035,7 @@ reg_ch1blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch1blopcr_load_o
reg_ch1rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -2069,7 +2069,7 @@ reg_ch1blopcr_load_o
</td>
<td class="td_pblock_right">
<b>CH2BLOPCR:</b>
<b>CH2RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2086,7 +2086,7 @@ reg_ch1blopcr_load_o
</td>
<td class="td_pblock_right">
reg_ch2blopcr_o[31:0]
reg_ch2rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2103,7 +2103,7 @@ reg_ch2blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch2blopcr_i[31:0]
reg_ch2rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2120,7 +2120,7 @@ reg_ch2blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch2blopcr_load_o
reg_ch2rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -2154,7 +2154,7 @@ reg_ch2blopcr_load_o
</td>
<td class="td_pblock_right">
<b>CH3BLOPCR:</b>
<b>CH3RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2171,7 +2171,7 @@ reg_ch2blopcr_load_o
</td>
<td class="td_pblock_right">
reg_ch3blopcr_o[31:0]
reg_ch3rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2188,7 +2188,7 @@ reg_ch3blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch3blopcr_i[31:0]
reg_ch3rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2205,7 +2205,7 @@ reg_ch3blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch3blopcr_load_o
reg_ch3rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -2239,7 +2239,7 @@ reg_ch3blopcr_load_o
</td>
<td class="td_pblock_right">
<b>CH4BLOPCR:</b>
<b>CH4RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2256,7 +2256,7 @@ reg_ch3blopcr_load_o
</td>
<td class="td_pblock_right">
reg_ch4blopcr_o[31:0]
reg_ch4rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2273,7 +2273,7 @@ reg_ch4blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch4blopcr_i[31:0]
reg_ch4rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2290,7 +2290,7 @@ reg_ch4blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch4blopcr_load_o
reg_ch4rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -2324,7 +2324,7 @@ reg_ch4blopcr_load_o
</td>
<td class="td_pblock_right">
<b>CH5BLOPCR:</b>
<b>CH5RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2341,7 +2341,7 @@ reg_ch4blopcr_load_o
</td>
<td class="td_pblock_right">
reg_ch5blopcr_o[31:0]
reg_ch5rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2358,7 +2358,7 @@ reg_ch5blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch5blopcr_i[31:0]
reg_ch5rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2375,7 +2375,7 @@ reg_ch5blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch5blopcr_load_o
reg_ch5rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -2409,7 +2409,7 @@ reg_ch5blopcr_load_o
</td>
<td class="td_pblock_right">
<b>CH6BLOPCR:</b>
<b>CH6RPPCR:</b>
</td>
<td class="td_arrow_right">
......@@ -2426,7 +2426,7 @@ reg_ch5blopcr_load_o
</td>
<td class="td_pblock_right">
reg_ch6blopcr_o[31:0]
reg_ch6rppcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2443,7 +2443,7 @@ reg_ch6blopcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch6blopcr_i[31:0]
reg_ch6rppcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2460,7 +2460,7 @@ reg_ch6blopcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch6blopcr_load_o
reg_ch6rppcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -5452,15 +5452,15 @@ MPT
</b>[<i>write-only</i>]: Manual Pulse Trigger
<br>Write the following sequence to trigger a pulse: <br> 0xde -- Byte 1 of magic sequence <br> 0xad -- Byte 2 of magic sequence <br> 0xbe -- Byte 3 of magic sequence <br> 0xef -- Byte 4 of magic sequence <br> Number in range 1..6 -- trigger a pulse
</ul>
<a name="CH1TTLPCR"></a>
<h3><a name="sect_3_5">3.5. CH1TTLPCR</a></h3>
<a name="CH1FPPCR"></a>
<h3><a name="sect_3_5">3.5. CH1FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch1ttlpcr
reg_ch1fppcr
</td>
</tr>
<tr>
......@@ -5476,7 +5476,7 @@ reg_ch1ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH1TTLPCR
CH1FPPCR
</td>
</tr>
<tr>
......@@ -5489,7 +5489,7 @@ CH1TTLPCR
</tr>
</table>
<p>
Channel 1 Pulse Counter Register for TTL pulses
Channel 1 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -5520,7 +5520,7 @@ Channel 1 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1TTLPCR[31:24]
CH1FPPCR[31:24]
</td>
<td >
......@@ -5574,7 +5574,7 @@ CH1TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1TTLPCR[23:16]
CH1FPPCR[23:16]
</td>
<td >
......@@ -5628,7 +5628,7 @@ CH1TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1TTLPCR[15:8]
CH1FPPCR[15:8]
</td>
<td >
......@@ -5682,7 +5682,7 @@ CH1TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1TTLPCR[7:0]
CH1FPPCR[7:0]
</td>
<td >
......@@ -5709,18 +5709,18 @@ CH1TTLPCR[7:0]
</table>
<ul>
<li><b>
CH1TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH1FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH2TTLPCR"></a>
<h3><a name="sect_3_6">3.6. CH2TTLPCR</a></h3>
<a name="CH2FPPCR"></a>
<h3><a name="sect_3_6">3.6. CH2FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch2ttlpcr
reg_ch2fppcr
</td>
</tr>
<tr>
......@@ -5736,7 +5736,7 @@ reg_ch2ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH2TTLPCR
CH2FPPCR
</td>
</tr>
<tr>
......@@ -5749,7 +5749,7 @@ CH2TTLPCR
</tr>
</table>
<p>
Channel 2 Pulse Counter Register for TTL pulses
Channel 2 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -5780,7 +5780,7 @@ Channel 2 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2TTLPCR[31:24]
CH2FPPCR[31:24]
</td>
<td >
......@@ -5834,7 +5834,7 @@ CH2TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2TTLPCR[23:16]
CH2FPPCR[23:16]
</td>
<td >
......@@ -5888,7 +5888,7 @@ CH2TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2TTLPCR[15:8]
CH2FPPCR[15:8]
</td>
<td >
......@@ -5942,7 +5942,7 @@ CH2TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2TTLPCR[7:0]
CH2FPPCR[7:0]
</td>
<td >
......@@ -5969,18 +5969,18 @@ CH2TTLPCR[7:0]
</table>
<ul>
<li><b>
CH2TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH2FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH3TTLPCR"></a>
<h3><a name="sect_3_7">3.7. CH3TTLPCR</a></h3>
<a name="CH3FPPCR"></a>
<h3><a name="sect_3_7">3.7. CH3FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch3ttlpcr
reg_ch3fppcr
</td>
</tr>
<tr>
......@@ -5996,7 +5996,7 @@ reg_ch3ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH3TTLPCR
CH3FPPCR
</td>
</tr>
<tr>
......@@ -6009,7 +6009,7 @@ CH3TTLPCR
</tr>
</table>
<p>
Channel 3 Pulse Counter Register for TTL pulses
Channel 3 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6040,7 +6040,7 @@ Channel 3 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3TTLPCR[31:24]
CH3FPPCR[31:24]
</td>
<td >
......@@ -6094,7 +6094,7 @@ CH3TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3TTLPCR[23:16]
CH3FPPCR[23:16]
</td>
<td >
......@@ -6148,7 +6148,7 @@ CH3TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3TTLPCR[15:8]
CH3FPPCR[15:8]
</td>
<td >
......@@ -6202,7 +6202,7 @@ CH3TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3TTLPCR[7:0]
CH3FPPCR[7:0]
</td>
<td >
......@@ -6229,18 +6229,18 @@ CH3TTLPCR[7:0]
</table>
<ul>
<li><b>
CH3TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH3FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH4TTLPCR"></a>
<h3><a name="sect_3_8">3.8. CH4TTLPCR</a></h3>
<a name="CH4FPPCR"></a>
<h3><a name="sect_3_8">3.8. CH4FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch4ttlpcr
reg_ch4fppcr
</td>
</tr>
<tr>
......@@ -6256,7 +6256,7 @@ reg_ch4ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH4TTLPCR
CH4FPPCR
</td>
</tr>
<tr>
......@@ -6269,7 +6269,7 @@ CH4TTLPCR
</tr>
</table>
<p>
Channel 4 Pulse Counter Register for TTL pulses
Channel 4 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6300,7 +6300,7 @@ Channel 4 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4TTLPCR[31:24]
CH4FPPCR[31:24]
</td>
<td >
......@@ -6354,7 +6354,7 @@ CH4TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4TTLPCR[23:16]
CH4FPPCR[23:16]
</td>
<td >
......@@ -6408,7 +6408,7 @@ CH4TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4TTLPCR[15:8]
CH4FPPCR[15:8]
</td>
<td >
......@@ -6462,7 +6462,7 @@ CH4TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4TTLPCR[7:0]
CH4FPPCR[7:0]
</td>
<td >
......@@ -6489,18 +6489,18 @@ CH4TTLPCR[7:0]
</table>
<ul>
<li><b>
CH4TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH4FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH5TTLPCR"></a>
<h3><a name="sect_3_9">3.9. CH5TTLPCR</a></h3>
<a name="CH5FPPCR"></a>
<h3><a name="sect_3_9">3.9. CH5FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch5ttlpcr
reg_ch5fppcr
</td>
</tr>
<tr>
......@@ -6516,7 +6516,7 @@ reg_ch5ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH5TTLPCR
CH5FPPCR
</td>
</tr>
<tr>
......@@ -6529,7 +6529,7 @@ CH5TTLPCR
</tr>
</table>
<p>
Channel 5 Pulse Counter Register for TTL pulses
Channel 5 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6560,7 +6560,7 @@ Channel 5 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5TTLPCR[31:24]
CH5FPPCR[31:24]
</td>
<td >
......@@ -6614,7 +6614,7 @@ CH5TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5TTLPCR[23:16]
CH5FPPCR[23:16]
</td>
<td >
......@@ -6668,7 +6668,7 @@ CH5TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5TTLPCR[15:8]
CH5FPPCR[15:8]
</td>
<td >
......@@ -6722,7 +6722,7 @@ CH5TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5TTLPCR[7:0]
CH5FPPCR[7:0]
</td>
<td >
......@@ -6749,18 +6749,18 @@ CH5TTLPCR[7:0]
</table>
<ul>
<li><b>
CH5TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH5FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH6TTLPCR"></a>
<h3><a name="sect_3_10">3.10. CH6TTLPCR</a></h3>
<a name="CH6FPPCR"></a>
<h3><a name="sect_3_10">3.10. CH6FPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch6ttlpcr
reg_ch6fppcr
</td>
</tr>
<tr>
......@@ -6776,7 +6776,7 @@ reg_ch6ttlpcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH6TTLPCR
CH6FPPCR
</td>
</tr>
<tr>
......@@ -6789,7 +6789,7 @@ CH6TTLPCR
</tr>
</table>
<p>
Channel 6 Pulse Counter Register for TTL pulses
Channel 6 Pulse Counter Register for front panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6820,7 +6820,7 @@ Channel 6 Pulse Counter Register for TTL pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6TTLPCR[31:24]
CH6FPPCR[31:24]
</td>
<td >
......@@ -6874,7 +6874,7 @@ CH6TTLPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6TTLPCR[23:16]
CH6FPPCR[23:16]
</td>
<td >
......@@ -6928,7 +6928,7 @@ CH6TTLPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6TTLPCR[15:8]
CH6FPPCR[15:8]
</td>
<td >
......@@ -6982,7 +6982,7 @@ CH6TTLPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6TTLPCR[7:0]
CH6FPPCR[7:0]
</td>
<td >
......@@ -7009,18 +7009,18 @@ CH6TTLPCR[7:0]
</table>
<ul>
<li><b>
CH6TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
CH6FPPCR
</b>[<i>read/write</i>]: Value of front panel pulse counter
</ul>
<a name="CH1BLOPCR"></a>
<h3><a name="sect_3_11">3.11. CH1BLOPCR</a></h3>
<a name="CH1RPPCR"></a>
<h3><a name="sect_3_11">3.11. CH1RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch1blopcr
reg_ch1rppcr
</td>
</tr>
<tr>
......@@ -7036,7 +7036,7 @@ reg_ch1blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH1BLOPCR
CH1RPPCR
</td>
</tr>
<tr>
......@@ -7049,7 +7049,7 @@ CH1BLOPCR
</tr>
</table>
<p>
Channel 1 Pulse Counter Register for BLO pulses
Channel 1 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7080,7 +7080,7 @@ Channel 1 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1BLOPCR[31:24]
CH1RPPCR[31:24]
</td>
<td >
......@@ -7134,7 +7134,7 @@ CH1BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1BLOPCR[23:16]
CH1RPPCR[23:16]
</td>
<td >
......@@ -7188,7 +7188,7 @@ CH1BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1BLOPCR[15:8]
CH1RPPCR[15:8]
</td>
<td >
......@@ -7242,7 +7242,7 @@ CH1BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1BLOPCR[7:0]
CH1RPPCR[7:0]
</td>
<td >
......@@ -7269,18 +7269,18 @@ CH1BLOPCR[7:0]
</table>
<ul>
<li><b>
CH1BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH1RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="CH2BLOPCR"></a>
<h3><a name="sect_3_12">3.12. CH2BLOPCR</a></h3>
<a name="CH2RPPCR"></a>
<h3><a name="sect_3_12">3.12. CH2RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch2blopcr
reg_ch2rppcr
</td>
</tr>
<tr>
......@@ -7296,7 +7296,7 @@ reg_ch2blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH2BLOPCR
CH2RPPCR
</td>
</tr>
<tr>
......@@ -7309,7 +7309,7 @@ CH2BLOPCR
</tr>
</table>
<p>
Channel 2 Pulse Counter Register for BLO pulses
Channel 2 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7340,7 +7340,7 @@ Channel 2 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2BLOPCR[31:24]
CH2RPPCR[31:24]
</td>
<td >
......@@ -7394,7 +7394,7 @@ CH2BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2BLOPCR[23:16]
CH2RPPCR[23:16]
</td>
<td >
......@@ -7448,7 +7448,7 @@ CH2BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2BLOPCR[15:8]
CH2RPPCR[15:8]
</td>
<td >
......@@ -7502,7 +7502,7 @@ CH2BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2BLOPCR[7:0]
CH2RPPCR[7:0]
</td>
<td >
......@@ -7529,18 +7529,18 @@ CH2BLOPCR[7:0]
</table>
<ul>
<li><b>
CH2BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH2RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="CH3BLOPCR"></a>
<h3><a name="sect_3_13">3.13. CH3BLOPCR</a></h3>
<a name="CH3RPPCR"></a>
<h3><a name="sect_3_13">3.13. CH3RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch3blopcr
reg_ch3rppcr
</td>
</tr>
<tr>
......@@ -7556,7 +7556,7 @@ reg_ch3blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH3BLOPCR
CH3RPPCR
</td>
</tr>
<tr>
......@@ -7569,7 +7569,7 @@ CH3BLOPCR
</tr>
</table>
<p>
Channel 3 Pulse Counter Register for BLO pulses
Channel 3 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7600,7 +7600,7 @@ Channel 3 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3BLOPCR[31:24]
CH3RPPCR[31:24]
</td>
<td >
......@@ -7654,7 +7654,7 @@ CH3BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3BLOPCR[23:16]
CH3RPPCR[23:16]
</td>
<td >
......@@ -7708,7 +7708,7 @@ CH3BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3BLOPCR[15:8]
CH3RPPCR[15:8]
</td>
<td >
......@@ -7762,7 +7762,7 @@ CH3BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3BLOPCR[7:0]
CH3RPPCR[7:0]
</td>
<td >
......@@ -7789,18 +7789,18 @@ CH3BLOPCR[7:0]
</table>
<ul>
<li><b>
CH3BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH3RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="CH4BLOPCR"></a>
<h3><a name="sect_3_14">3.14. CH4BLOPCR</a></h3>
<a name="CH4RPPCR"></a>
<h3><a name="sect_3_14">3.14. CH4RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch4blopcr
reg_ch4rppcr
</td>
</tr>
<tr>
......@@ -7816,7 +7816,7 @@ reg_ch4blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH4BLOPCR
CH4RPPCR
</td>
</tr>
<tr>
......@@ -7829,7 +7829,7 @@ CH4BLOPCR
</tr>
</table>
<p>
Channel 4 Pulse Counter Register for BLO pulses
Channel 4 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7860,7 +7860,7 @@ Channel 4 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4BLOPCR[31:24]
CH4RPPCR[31:24]
</td>
<td >
......@@ -7914,7 +7914,7 @@ CH4BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4BLOPCR[23:16]
CH4RPPCR[23:16]
</td>
<td >
......@@ -7968,7 +7968,7 @@ CH4BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4BLOPCR[15:8]
CH4RPPCR[15:8]
</td>
<td >
......@@ -8022,7 +8022,7 @@ CH4BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4BLOPCR[7:0]
CH4RPPCR[7:0]
</td>
<td >
......@@ -8049,18 +8049,18 @@ CH4BLOPCR[7:0]
</table>
<ul>
<li><b>
CH4BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH4RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="CH5BLOPCR"></a>
<h3><a name="sect_3_15">3.15. CH5BLOPCR</a></h3>
<a name="CH5RPPCR"></a>
<h3><a name="sect_3_15">3.15. CH5RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch5blopcr
reg_ch5rppcr
</td>
</tr>
<tr>
......@@ -8076,7 +8076,7 @@ reg_ch5blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH5BLOPCR
CH5RPPCR
</td>
</tr>
<tr>
......@@ -8089,7 +8089,7 @@ CH5BLOPCR
</tr>
</table>
<p>
Channel 5 Pulse Counter Register for BLO pulses
Channel 5 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -8120,7 +8120,7 @@ Channel 5 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5BLOPCR[31:24]
CH5RPPCR[31:24]
</td>
<td >
......@@ -8174,7 +8174,7 @@ CH5BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5BLOPCR[23:16]
CH5RPPCR[23:16]
</td>
<td >
......@@ -8228,7 +8228,7 @@ CH5BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5BLOPCR[15:8]
CH5RPPCR[15:8]
</td>
<td >
......@@ -8282,7 +8282,7 @@ CH5BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH5BLOPCR[7:0]
CH5RPPCR[7:0]
</td>
<td >
......@@ -8309,18 +8309,18 @@ CH5BLOPCR[7:0]
</table>
<ul>
<li><b>
CH5BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH5RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="CH6BLOPCR"></a>
<h3><a name="sect_3_16">3.16. CH6BLOPCR</a></h3>
<a name="CH6RPPCR"></a>
<h3><a name="sect_3_16">3.16. CH6RPPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_ch6blopcr
reg_ch6rppcr
</td>
</tr>
<tr>
......@@ -8336,7 +8336,7 @@ reg_ch6blopcr
<b>C prefix: </b>
</td>
<td class="td_code">
CH6BLOPCR
CH6RPPCR
</td>
</tr>
<tr>
......@@ -8349,7 +8349,7 @@ CH6BLOPCR
</tr>
</table>
<p>
Channel 6 Pulse Counter Register for BLO pulses
Channel 6 Pulse Counter Register for rear panel pulses
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -8380,7 +8380,7 @@ Channel 6 Pulse Counter Register for BLO pulses
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6BLOPCR[31:24]
CH6RPPCR[31:24]
</td>
<td >
......@@ -8434,7 +8434,7 @@ CH6BLOPCR[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6BLOPCR[23:16]
CH6RPPCR[23:16]
</td>
<td >
......@@ -8488,7 +8488,7 @@ CH6BLOPCR[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6BLOPCR[15:8]
CH6RPPCR[15:8]
</td>
<td >
......@@ -8542,7 +8542,7 @@ CH6BLOPCR[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH6BLOPCR[7:0]
CH6RPPCR[7:0]
</td>
<td >
......@@ -8569,8 +8569,8 @@ CH6BLOPCR[7:0]
</table>
<ul>
<li><b>
CH6BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
CH6RPPCR
</b>[<i>read/write</i>]: Rear panel pulse counter value
</ul>
<a name="TVLR"></a>
<h3><a name="sect_3_17">3.17. TVLR</a></h3>
......
modules/conv_regs.tex
View file @ 9b832b6a
......@@ -12,18 +12,18 @@
0x4& REG & SR & reg\_sr & SR\\
0x8& REG & ERR & reg\_err & ERR\\
0xc& REG & CR & reg\_cr & CR\\
0x10& REG & CH1TTLPCR & reg\_ch1ttlpcr & CH1TTLPCR\\
0x14& REG & CH2TTLPCR & reg\_ch2ttlpcr & CH2TTLPCR\\
0x18& REG & CH3TTLPCR & reg\_ch3ttlpcr & CH3TTLPCR\\
0x1c& REG & CH4TTLPCR & reg\_ch4ttlpcr & CH4TTLPCR\\
0x20& REG & CH5TTLPCR & reg\_ch5ttlpcr & CH5TTLPCR\\
0x24& REG & CH6TTLPCR & reg\_ch6ttlpcr & CH6TTLPCR\\
0x28& REG & CH1BLOPCR & reg\_ch1blopcr & CH1BLOPCR\\
0x2c& REG & CH2BLOPCR & reg\_ch2blopcr & CH2BLOPCR\\
0x30& REG & CH3BLOPCR & reg\_ch3blopcr & CH3BLOPCR\\
0x34& REG & CH4BLOPCR & reg\_ch4blopcr & CH4BLOPCR\\
0x38& REG & CH5BLOPCR & reg\_ch5blopcr & CH5BLOPCR\\
0x3c& REG & CH6BLOPCR & reg\_ch6blopcr & CH6BLOPCR\\
0x10& REG & CH1FPPCR & reg\_ch1fppcr & CH1FPPCR\\
0x14& REG & CH2FPPCR & reg\_ch2fppcr & CH2FPPCR\\
0x18& REG & CH3FPPCR & reg\_ch3fppcr & CH3FPPCR\\
0x1c& REG & CH4FPPCR & reg\_ch4fppcr & CH4FPPCR\\
0x20& REG & CH5FPPCR & reg\_ch5fppcr & CH5FPPCR\\
0x24& REG & CH6FPPCR & reg\_ch6fppcr & CH6FPPCR\\
0x28& REG & CH1RPPCR & reg\_ch1rppcr & CH1RPPCR\\
0x2c& REG & CH2RPPCR & reg\_ch2rppcr & CH2RPPCR\\
0x30& REG & CH3RPPCR & reg\_ch3rppcr & CH3RPPCR\\
0x34& REG & CH4RPPCR & reg\_ch4rppcr & CH4RPPCR\\
0x38& REG & CH5RPPCR & reg\_ch5rppcr & CH5RPPCR\\
0x3c& REG & CH6RPPCR & reg\_ch6rppcr & CH6RPPCR\\
0x40& REG & TVLR & reg\_tvlr & TVLR\\
0x44& REG & TVHR & reg\_tvhr & TVHR\\
0x48& REG & TBMR & reg\_tbmr & TBMR\\
......@@ -300,18 +300,18 @@ MPT
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\end{itemize}
\paragraph*{CH1TTLPCR}\vspace{12pt}
\paragraph*{CH1FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch1ttlpcr\\
{\bf HW prefix:} & reg\_ch1fppcr\\
{\bf HW address:} & 0x4\\
{\bf SW prefix:} & CH1TTLPCR\\
{\bf SW prefix:} & CH1FPPCR\\
{\bf SW offset:} & 0x10\\
\end{tabular}
\vspace{12pt}
Channel 1 Pulse Counter Register for TTL pulses
Channel 1 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -319,19 +319,19 @@ Channel 1 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -339,22 +339,22 @@ Channel 1 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH1TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH1FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH2TTLPCR}\vspace{12pt}
\paragraph*{CH2FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch2ttlpcr\\
{\bf HW prefix:} & reg\_ch2fppcr\\
{\bf HW address:} & 0x5\\
{\bf SW prefix:} & CH2TTLPCR\\
{\bf SW prefix:} & CH2FPPCR\\
{\bf SW offset:} & 0x14\\
\end{tabular}
\vspace{12pt}
Channel 2 Pulse Counter Register for TTL pulses
Channel 2 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -362,19 +362,19 @@ Channel 2 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -382,22 +382,22 @@ Channel 2 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH2TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH2FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH3TTLPCR}\vspace{12pt}
\paragraph*{CH3FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch3ttlpcr\\
{\bf HW prefix:} & reg\_ch3fppcr\\
{\bf HW address:} & 0x6\\
{\bf SW prefix:} & CH3TTLPCR\\
{\bf SW prefix:} & CH3FPPCR\\
{\bf SW offset:} & 0x18\\
\end{tabular}
\vspace{12pt}
Channel 3 Pulse Counter Register for TTL pulses
Channel 3 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -405,19 +405,19 @@ Channel 3 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -425,22 +425,22 @@ Channel 3 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH3TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH3FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH4TTLPCR}\vspace{12pt}
\paragraph*{CH4FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch4ttlpcr\\
{\bf HW prefix:} & reg\_ch4fppcr\\
{\bf HW address:} & 0x7\\
{\bf SW prefix:} & CH4TTLPCR\\
{\bf SW prefix:} & CH4FPPCR\\
{\bf SW offset:} & 0x1c\\
\end{tabular}
\vspace{12pt}
Channel 4 Pulse Counter Register for TTL pulses
Channel 4 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -448,19 +448,19 @@ Channel 4 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -468,22 +468,22 @@ Channel 4 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH4TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH4FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH5TTLPCR}\vspace{12pt}
\paragraph*{CH5FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch5ttlpcr\\
{\bf HW prefix:} & reg\_ch5fppcr\\
{\bf HW address:} & 0x8\\
{\bf SW prefix:} & CH5TTLPCR\\
{\bf SW prefix:} & CH5FPPCR\\
{\bf SW offset:} & 0x20\\
\end{tabular}
\vspace{12pt}
Channel 5 Pulse Counter Register for TTL pulses
Channel 5 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -491,19 +491,19 @@ Channel 5 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -511,22 +511,22 @@ Channel 5 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH5TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH5FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH6TTLPCR}\vspace{12pt}
\paragraph*{CH6FPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch6ttlpcr\\
{\bf HW prefix:} & reg\_ch6fppcr\\
{\bf HW address:} & 0x9\\
{\bf SW prefix:} & CH6TTLPCR\\
{\bf SW prefix:} & CH6FPPCR\\
{\bf SW offset:} & 0x24\\
\end{tabular}
\vspace{12pt}
Channel 6 Pulse Counter Register for TTL pulses
Channel 6 Pulse Counter Register for front panel pulses
\vspace{12pt}
\noindent
......@@ -534,19 +534,19 @@ Channel 6 Pulse Counter Register for TTL pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6FPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6FPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6FPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6TTLPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6FPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -554,22 +554,22 @@ Channel 6 Pulse Counter Register for TTL pulses
\begin{itemize}
\item \begin{small}
{\bf
CH6TTLPCR
} [\emph{read/write}]: TTL pulse counter value
CH6FPPCR
} [\emph{read/write}]: Value of front panel pulse counter
\end{small}
\end{itemize}
\paragraph*{CH1BLOPCR}\vspace{12pt}
\paragraph*{CH1RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch1blopcr\\
{\bf HW prefix:} & reg\_ch1rppcr\\
{\bf HW address:} & 0xa\\
{\bf SW prefix:} & CH1BLOPCR\\
{\bf SW prefix:} & CH1RPPCR\\
{\bf SW offset:} & 0x28\\
\end{tabular}
\vspace{12pt}
Channel 1 Pulse Counter Register for BLO pulses
Channel 1 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -577,19 +577,19 @@ Channel 1 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH1RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -597,22 +597,22 @@ Channel 1 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH1BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH1RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{CH2BLOPCR}\vspace{12pt}
\paragraph*{CH2RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch2blopcr\\
{\bf HW prefix:} & reg\_ch2rppcr\\
{\bf HW address:} & 0xb\\
{\bf SW prefix:} & CH2BLOPCR\\
{\bf SW prefix:} & CH2RPPCR\\
{\bf SW offset:} & 0x2c\\
\end{tabular}
\vspace{12pt}
Channel 2 Pulse Counter Register for BLO pulses
Channel 2 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -620,19 +620,19 @@ Channel 2 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH2RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -640,22 +640,22 @@ Channel 2 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH2BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH2RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{CH3BLOPCR}\vspace{12pt}
\paragraph*{CH3RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch3blopcr\\
{\bf HW prefix:} & reg\_ch3rppcr\\
{\bf HW address:} & 0xc\\
{\bf SW prefix:} & CH3BLOPCR\\
{\bf SW prefix:} & CH3RPPCR\\
{\bf SW offset:} & 0x30\\
\end{tabular}
\vspace{12pt}
Channel 3 Pulse Counter Register for BLO pulses
Channel 3 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -663,19 +663,19 @@ Channel 3 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH3RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -683,22 +683,22 @@ Channel 3 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH3BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH3RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{CH4BLOPCR}\vspace{12pt}
\paragraph*{CH4RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch4blopcr\\
{\bf HW prefix:} & reg\_ch4rppcr\\
{\bf HW address:} & 0xd\\
{\bf SW prefix:} & CH4BLOPCR\\
{\bf SW prefix:} & CH4RPPCR\\
{\bf SW offset:} & 0x34\\
\end{tabular}
\vspace{12pt}
Channel 4 Pulse Counter Register for BLO pulses
Channel 4 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -706,19 +706,19 @@ Channel 4 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH4RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -726,22 +726,22 @@ Channel 4 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH4BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH4RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{CH5BLOPCR}\vspace{12pt}
\paragraph*{CH5RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch5blopcr\\
{\bf HW prefix:} & reg\_ch5rppcr\\
{\bf HW address:} & 0xe\\
{\bf SW prefix:} & CH5BLOPCR\\
{\bf SW prefix:} & CH5RPPCR\\
{\bf SW offset:} & 0x38\\
\end{tabular}
\vspace{12pt}
Channel 5 Pulse Counter Register for BLO pulses
Channel 5 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -749,19 +749,19 @@ Channel 5 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH5RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -769,22 +769,22 @@ Channel 5 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH5BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH5RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{CH6BLOPCR}\vspace{12pt}
\paragraph*{CH6RPPCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & reg\_ch6blopcr\\
{\bf HW prefix:} & reg\_ch6rppcr\\
{\bf HW address:} & 0xf\\
{\bf SW prefix:} & CH6BLOPCR\\
{\bf SW prefix:} & CH6RPPCR\\
{\bf SW offset:} & 0x3c\\
\end{tabular}
\vspace{12pt}
Channel 6 Pulse Counter Register for BLO pulses
Channel 6 Pulse Counter Register for rear panel pulses
\vspace{12pt}
\noindent
......@@ -792,19 +792,19 @@ Channel 6 Pulse Counter Register for BLO pulses
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6RPPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6RPPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6RPPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6BLOPCR[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CH6RPPCR[7:0]}\\
\hline
\end{tabular}
}
......@@ -812,8 +812,8 @@ Channel 6 Pulse Counter Register for BLO pulses
\begin{itemize}
\item \begin{small}
{\bf
CH6BLOPCR
} [\emph{read/write}]: BLO pulse counter value
CH6RPPCR
} [\emph{read/write}]: Rear panel pulse counter value
\end{small}
\end{itemize}
\paragraph*{TVLR}\vspace{12pt}
......
modules/conv_regs.vhd
View file @ 9b832b6a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : .\conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : 02/06/17 15:05:15
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from .\conv_regs.wb
-- Created : 09/26/17 10:50:26
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -66,54 +66,54 @@ entity conv_regs is
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH1TTLPCR'
reg_ch1ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch1ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch1ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH2TTLPCR'
reg_ch2ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch2ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch2ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH3TTLPCR'
reg_ch3ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch3ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch3ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH4TTLPCR'
reg_ch4ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch4ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch4ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH5TTLPCR'
reg_ch5ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch5ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch5ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR'
reg_ch6ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch6ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch6ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR'
reg_ch1blopcr_o : out std_logic_vector(31 downto 0);
reg_ch1blopcr_i : in std_logic_vector(31 downto 0);
reg_ch1blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH2BLOPCR'
reg_ch2blopcr_o : out std_logic_vector(31 downto 0);
reg_ch2blopcr_i : in std_logic_vector(31 downto 0);
reg_ch2blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH3BLOPCR'
reg_ch3blopcr_o : out std_logic_vector(31 downto 0);
reg_ch3blopcr_i : in std_logic_vector(31 downto 0);
reg_ch3blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH4BLOPCR'
reg_ch4blopcr_o : out std_logic_vector(31 downto 0);
reg_ch4blopcr_i : in std_logic_vector(31 downto 0);
reg_ch4blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH5BLOPCR'
reg_ch5blopcr_o : out std_logic_vector(31 downto 0);
reg_ch5blopcr_i : in std_logic_vector(31 downto 0);
reg_ch5blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH6BLOPCR'
reg_ch6blopcr_o : out std_logic_vector(31 downto 0);
reg_ch6blopcr_i : in std_logic_vector(31 downto 0);
reg_ch6blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1fppcr_o : out std_logic_vector(31 downto 0);
reg_ch1fppcr_i : in std_logic_vector(31 downto 0);
reg_ch1fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2fppcr_o : out std_logic_vector(31 downto 0);
reg_ch2fppcr_i : in std_logic_vector(31 downto 0);
reg_ch2fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3fppcr_o : out std_logic_vector(31 downto 0);
reg_ch3fppcr_i : in std_logic_vector(31 downto 0);
reg_ch3fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4fppcr_o : out std_logic_vector(31 downto 0);
reg_ch4fppcr_i : in std_logic_vector(31 downto 0);
reg_ch4fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5fppcr_o : out std_logic_vector(31 downto 0);
reg_ch5fppcr_i : in std_logic_vector(31 downto 0);
reg_ch5fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6fppcr_o : out std_logic_vector(31 downto 0);
reg_ch6fppcr_i : in std_logic_vector(31 downto 0);
reg_ch6fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1rppcr_o : out std_logic_vector(31 downto 0);
reg_ch1rppcr_i : in std_logic_vector(31 downto 0);
reg_ch1rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2rppcr_o : out std_logic_vector(31 downto 0);
reg_ch2rppcr_i : in std_logic_vector(31 downto 0);
reg_ch2rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3rppcr_o : out std_logic_vector(31 downto 0);
reg_ch3rppcr_i : in std_logic_vector(31 downto 0);
reg_ch3rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4rppcr_o : out std_logic_vector(31 downto 0);
reg_ch4rppcr_i : in std_logic_vector(31 downto 0);
reg_ch4rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5rppcr_o : out std_logic_vector(31 downto 0);
reg_ch5rppcr_i : in std_logic_vector(31 downto 0);
reg_ch5rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6rppcr_o : out std_logic_vector(31 downto 0);
reg_ch6rppcr_i : in std_logic_vector(31 downto 0);
reg_ch6rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
......@@ -250,18 +250,18 @@ begin
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1ttlpcr_load_o <= '0';
reg_ch2ttlpcr_load_o <= '0';
reg_ch3ttlpcr_load_o <= '0';
reg_ch4ttlpcr_load_o <= '0';
reg_ch5ttlpcr_load_o <= '0';
reg_ch6ttlpcr_load_o <= '0';
reg_ch1blopcr_load_o <= '0';
reg_ch2blopcr_load_o <= '0';
reg_ch3blopcr_load_o <= '0';
reg_ch4blopcr_load_o <= '0';
reg_ch5blopcr_load_o <= '0';
reg_ch6blopcr_load_o <= '0';
reg_ch1fppcr_load_o <= '0';
reg_ch2fppcr_load_o <= '0';
reg_ch3fppcr_load_o <= '0';
reg_ch4fppcr_load_o <= '0';
reg_ch5fppcr_load_o <= '0';
reg_ch6fppcr_load_o <= '0';
reg_ch1rppcr_load_o <= '0';
reg_ch2rppcr_load_o <= '0';
reg_ch3rppcr_load_o <= '0';
reg_ch4rppcr_load_o <= '0';
reg_ch5rppcr_load_o <= '0';
reg_ch6rppcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
......@@ -279,18 +279,18 @@ begin
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1ttlpcr_load_o <= '0';
reg_ch2ttlpcr_load_o <= '0';
reg_ch3ttlpcr_load_o <= '0';
reg_ch4ttlpcr_load_o <= '0';
reg_ch5ttlpcr_load_o <= '0';
reg_ch6ttlpcr_load_o <= '0';
reg_ch1blopcr_load_o <= '0';
reg_ch2blopcr_load_o <= '0';
reg_ch3blopcr_load_o <= '0';
reg_ch4blopcr_load_o <= '0';
reg_ch5blopcr_load_o <= '0';
reg_ch6blopcr_load_o <= '0';
reg_ch1fppcr_load_o <= '0';
reg_ch2fppcr_load_o <= '0';
reg_ch3fppcr_load_o <= '0';
reg_ch4fppcr_load_o <= '0';
reg_ch5fppcr_load_o <= '0';
reg_ch6fppcr_load_o <= '0';
reg_ch1rppcr_load_o <= '0';
reg_ch2rppcr_load_o <= '0';
reg_ch3rppcr_load_o <= '0';
reg_ch4rppcr_load_o <= '0';
reg_ch5rppcr_load_o <= '0';
reg_ch6rppcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
......@@ -304,18 +304,18 @@ begin
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1ttlpcr_load_o <= '0';
reg_ch2ttlpcr_load_o <= '0';
reg_ch3ttlpcr_load_o <= '0';
reg_ch4ttlpcr_load_o <= '0';
reg_ch5ttlpcr_load_o <= '0';
reg_ch6ttlpcr_load_o <= '0';
reg_ch1blopcr_load_o <= '0';
reg_ch2blopcr_load_o <= '0';
reg_ch3blopcr_load_o <= '0';
reg_ch4blopcr_load_o <= '0';
reg_ch5blopcr_load_o <= '0';
reg_ch6blopcr_load_o <= '0';
reg_ch1fppcr_load_o <= '0';
reg_ch2fppcr_load_o <= '0';
reg_ch3fppcr_load_o <= '0';
reg_ch4fppcr_load_o <= '0';
reg_ch5fppcr_load_o <= '0';
reg_ch6fppcr_load_o <= '0';
reg_ch1rppcr_load_o <= '0';
reg_ch2rppcr_load_o <= '0';
reg_ch3rppcr_load_o <= '0';
reg_ch4rppcr_load_o <= '0';
reg_ch5rppcr_load_o <= '0';
reg_ch6rppcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
......@@ -415,86 +415,86 @@ begin
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
reg_ch1ttlpcr_load_o <= '1';
reg_ch1fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch1fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
reg_ch2ttlpcr_load_o <= '1';
reg_ch2fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch2fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
reg_ch3ttlpcr_load_o <= '1';
reg_ch3fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch3fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
reg_ch4ttlpcr_load_o <= '1';
reg_ch4fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch4fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
reg_ch5ttlpcr_load_o <= '1';
reg_ch5fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch5fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
reg_ch6ttlpcr_load_o <= '1';
reg_ch6fppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6ttlpcr_i;
rddata_reg(31 downto 0) <= reg_ch6fppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
reg_ch1blopcr_load_o <= '1';
reg_ch1rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1blopcr_i;
rddata_reg(31 downto 0) <= reg_ch1rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
reg_ch2blopcr_load_o <= '1';
reg_ch2rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2blopcr_i;
rddata_reg(31 downto 0) <= reg_ch2rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
reg_ch3blopcr_load_o <= '1';
reg_ch3rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3blopcr_i;
rddata_reg(31 downto 0) <= reg_ch3rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
reg_ch4blopcr_load_o <= '1';
reg_ch4rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4blopcr_i;
rddata_reg(31 downto 0) <= reg_ch4rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
if (wb_we_i = '1') then
reg_ch5blopcr_load_o <= '1';
reg_ch5rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5blopcr_i;
rddata_reg(31 downto 0) <= reg_ch5rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
reg_ch6blopcr_load_o <= '1';
reg_ch6rppcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6blopcr_i;
rddata_reg(31 downto 0) <= reg_ch6rppcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
......@@ -1007,30 +1007,30 @@ begin
-- Manual Pulse Trigger
-- pass-through field: Manual Pulse Trigger in register: CR
reg_cr_mpt_o <= wrdata_reg(9 downto 2);
-- TTL pulse counter value
reg_ch1ttlpcr_o <= wrdata_reg(31 downto 0);
-- TTL pulse counter value
reg_ch2ttlpcr_o <= wrdata_reg(31 downto 0);
-- TTL pulse counter value
reg_ch3ttlpcr_o <= wrdata_reg(31 downto 0);
-- TTL pulse counter value
reg_ch4ttlpcr_o <= wrdata_reg(31 downto 0);
-- TTL pulse counter value
reg_ch5ttlpcr_o <= wrdata_reg(31 downto 0);
-- TTL pulse counter value
reg_ch6ttlpcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch1blopcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch2blopcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch3blopcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch4blopcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch5blopcr_o <= wrdata_reg(31 downto 0);
-- BLO pulse counter value
reg_ch6blopcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch1fppcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch2fppcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch3fppcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch4fppcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch5fppcr_o <= wrdata_reg(31 downto 0);
-- Value of front panel pulse counter
reg_ch6fppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch1rppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch2rppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch3rppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch4rppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch5rppcr_o <= wrdata_reg(31 downto 0);
-- Rear panel pulse counter value
reg_ch6rppcr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 31..0
reg_tvlr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 39..32
......
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