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conv-common-gw
Commit 3a692ef1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add manual pulse trigger and thermometer

parent c1d3f39b
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modules/conv_man_trig.vhd
View file @ 3a692ef1
......@@ -73,9 +73,8 @@ entity conv_man_trig is
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse generator glitch filter, needed to generate a long
-- enough pulse
g_gf_len : positive := 1
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
);
port
(
......@@ -87,7 +86,7 @@ entity conv_man_trig is
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
-- Trigger output, g_pwidth long
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end entity conv_man_trig;
......@@ -143,8 +142,8 @@ architecture behav of conv_man_trig is
-- Signal for the current state of the FSM
signal state : t_state;
-- Counter to extend the pulse to the needed number of channels
signal cnt : unsigned(f_log2_size(g_gf_len)-1 downto 0);
-- Counter to create a pulse with width g_pwidth
signal cnt : unsigned(f_log2_size(g_pwidth)-1 downto 0);
--==============================================================================
-- architecture begin
......@@ -184,7 +183,7 @@ begin
end if;
when GEN =>
cnt <= cnt + 1;
if (cnt = g_gf_len-1) then
if (cnt = g_pwidth-1) then
state <= IDLE;
end if;
when others =>
......
top/conv_common_gw.vhd
View file @ 3a692ef1
......@@ -81,10 +81,17 @@ entity conv_common_gw is
g_pgen_gf_len : integer := 4;
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean;
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse counters
g_with_pulse_timetag : boolean;
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
......@@ -175,6 +182,9 @@ entity conv_common_gw is
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
......@@ -186,23 +196,12 @@ end entity conv_common_gw;
architecture arch of conv_common_gw is
--============================================================================
-- Type declarations
--============================================================================
-- Max. channel count of 6 enforced here:
type t_pulse_led_cnt is array(5 downto 0) of unsigned(18 downto 0);
type t_pulse_cnt is array(5 downto 0) of unsigned(31 downto 0);
type t_ch_pcr is array(5 downto 0) of std_logic_vector(31 downto 0);
type t_latest_timestamp_tai is array(5 downto 0) of std_logic_vector(39 downto 0);
type t_latest_timestamp_cycles is array(5 downto 0) of std_logic_vector(27 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
......@@ -212,21 +211,40 @@ architecture arch of conv_common_gw is
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000100";
constant c_addr_onewire_mst : t_wishbone_address := x"000000c0";
constant c_addr_sdb : t_wishbone_address := x"00000200";
constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
constant c_addr_sdb : t_wishbone_address := x"00000f00";
-- SDB interconnect layout
-- c_conv_regs_sdb defined in conv_common_gw_pkg.vhd
constant c_sdb_layout : t_sdb_record_array(c_nr_slaves-1 downto 0) := (
c_slv_conv_regs => f_sdb_embed_device(c_conv_regs_sdb, c_addr_conv_regs),
c_slv_multiboot => f_sdb_embed_device(c_xwb_xil_multiboot_sdb, c_addr_multiboot)
c_slv_multiboot => f_sdb_embed_device(c_xwb_xil_multiboot_sdb,
c_addr_multiboot),
c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
c_addr_onewire_mst)
);
-- Tag bufferdata width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- 6 -- channel mask for max. nr. channels
constant c_tagbuff_data_width : positive := 40 + 28 + 1 + 6;
-- xx -- channel mask for max. nr. channels
constant c_tagbuff_data_width : positive := 40 + 28 + 1 + c_max_nr_chans;
--============================================================================
-- Type declarations
--============================================================================
-- Max. channel count of c_max_nr_chans enforced here:
type t_pulse_led_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(18 downto 0);
type t_pulse_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(31 downto 0);
type t_ch_pcr is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(31 downto 0);
type t_latest_timestamp_tai is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(39 downto 0);
type t_latest_timestamp_cycles is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(27 downto 0);
--============================================================================
-- Signal declarations
......@@ -243,6 +261,7 @@ architecture arch of conv_common_gw is
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -273,12 +292,12 @@ architecture arch of conv_common_gw is
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal pmisse_bit : std_logic_vector(5 downto 0);
signal pmisse_bit_rst : std_logic_vector(5 downto 0);
signal pmisse_bit : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(5 downto 0);
signal ch_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
......@@ -289,9 +308,9 @@ architecture arch of conv_common_gw is
signal i2c_err_bit : std_logic;
signal i2c_err_bit_rst : std_logic;
signal i2c_err_bit_rst_ld : std_logic;
signal line_front : std_logic_vector(5 downto 0);
signal line_rear : std_logic_vector(5 downto 0);
signal line_rear_fs : std_logic_vector(5 downto 0);
signal line_front : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear_fs : std_logic_vector(c_max_nr_chans-1 downto 0);
-- LED signals
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -325,10 +344,14 @@ architecture arch of conv_common_gw is
signal buf_dat_out : std_logic_vector(c_tagbuff_data_width-1 downto 0);
-- Latest timestamp signals
signal latest_timestamp_ld : std_logic_vector(5 downto 0);
signal latest_timestamp_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal latest_timestamp_tai : t_latest_timestamp_tai;
signal latest_timestamp_cycles : t_latest_timestamp_cycles;
signal latest_timestamp_wrtag : std_logic_vector(5 downto 0);
signal latest_timestamp_wrtag : std_logic_vector(c_max_nr_chans-1 downto 0);
-- One-wire master signals
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
--==============================================================================
-- architecture begin
......@@ -422,6 +445,34 @@ begin
--============================================================================
trig_a <= pulse_i;
--------------------------------------------------------------------------------
gen_man_trig : if (g_with_man_trig = true) generate
-- Manual trigger logic
cmp_man_trig : conv_man_trig
generic map
(
g_nr_chan => g_nr_chans,
g_pwidth => g_man_trig_pwidth
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
reg_ld_i => mpt_ld,
reg_i => mpt,
trig_o => trig_man
);
end generate gen_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_no_man_trig : if (g_with_man_trig = false) generate
trig_man <= (others => '0');
end generate gen_no_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
......@@ -481,6 +532,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
ppulse_o => trig_chan_redge_p(i)
);
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
-- First, the pulse counters for the used channes (up to g_nr_chans)
......@@ -497,15 +549,18 @@ gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
end if;
end process p_pulse_cnt;
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < 6) generate
pulse_cnt(5 downto g_nr_chans) <= (others => (others => '0'));
--------------------------------------------------------------------------------
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_pulse_cnt_unused_chans;
--------------------------------------------------------------------------------
end generate gen_pulse_cnt;
--------------------------------------------------------------------------------
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i);
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-- Instantiate pulse generator block for the channel
cmp_pulse_gen : conv_pulse_gen
......@@ -562,7 +617,11 @@ end generate gen_pulse_cnt;
end process p_pulse_led;
end generate gen_pulse_chan_logic;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_pulse_timetag : if (g_with_pulse_timetag = true) generate
cmp_pulse_timetag : conv_pulse_timetag
generic map
......@@ -602,14 +661,16 @@ gen_pulse_timetag : if (g_with_pulse_timetag = true) generate
buf_wr_req_p_o => buf_wr_req_p
);
-- Assign ring buffer component inputs
gen_buf_chan : if (g_nr_chans = 6) generate
buf_dat_in( 5 downto 0) <= buf_chan;
--------------------------------------------------------------------------------
gen_buf_chan : if (g_nr_chans = c_max_nr_chans) generate
buf_dat_in(c_max_nr_chans-1 downto 0) <= buf_chan;
end generate gen_buf_chan;
gen_buf_chan_unused_chans: if (g_nr_chans < 6) generate
gen_buf_chan_unused_chans: if (g_nr_chans < c_max_nr_chans) generate
buf_dat_in(g_nr_chans-1 downto 0) <= buf_chan;
buf_dat_in(5 downto g_nr_chans) <= (others => '0');
buf_dat_in(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_buf_chan_unused_chans;
--------------------------------------------------------------------------------
buf_dat_in( 6) <= buf_wrtag;
buf_dat_in(34 downto 7) <= tm_cycles;
......@@ -643,6 +704,8 @@ end generate gen_buf_chan_unused_chans;
);
end generate gen_pulse_timetag;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Channel output assignments
pulse_o <= pulse_outp;
......@@ -807,21 +870,27 @@ end generate gen_pulse_timetag;
-- RTM lines combo
rtm_lines <= rtmp_i & rtmm_i;
-- Adapt line status regs according to number of channels (MAX. 6)
gen_line : if (g_nr_chans = 6) generate
line_front <= line_front_i;
line_rear <= line_rear_i;
--------------------------------------------------------------------------------
gen_line : if (g_nr_chans = c_max_nr_chans) generate
line_front <= line_front_i;
line_rear <= line_rear_i;
line_rear_fs <= line_rear_fs_i;
end generate gen_line;
--------------------------------------------------------------------------------
gen_line_unused_chans : if (g_nr_chans < 6) generate
--------------------------------------------------------------------------------
gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
-- connect used lines
line_front(g_nr_chans-1 downto 0) <= line_front_i;
line_front(5 downto g_nr_chans) <= (others => '0');
line_rear(g_nr_chans-1 downto 0) <= line_rear_i;
line_rear(5 downto g_nr_chans) <= (others => '0');
line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i;
line_rear_fs(5 downto g_nr_chans) <= (others => '0');
-- unused lines to zeroes
line_front(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_line_unused_chans;
--------------------------------------------------------------------------------
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
......@@ -871,10 +940,12 @@ end generate gen_line_unused_chans;
end if;
end process p_sr_pmisse_bit;
-- Set the rest of the PMISSE bits to zero when g_nr_chans < 6
gen_pmisse_unused_chans : if (g_nr_chans < 6) generate
pmisse_bit(5 downto g_nr_chans) <= (others => '0');
--------------------------------------------------------------------------------
-- Set the rest of the PMISSE bits to zero when g_nr_chans < c_max_nr_chans
gen_pmisse_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pmisse_bit(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate;
--------------------------------------------------------------------------------
-- Synchronize WR valid signal to implement the WRPRES bit
cmp_wrpres_sync : gc_sync_ffs
......@@ -924,12 +995,14 @@ end generate;
end if;
end process p_latest_timestamp;
--------------------------------------------------------------------------------
-- Connect unused timestamps to all zeroes
gen_latest_timestamp_unused_chans : if (g_nr_chans < 6) generate
latest_timestamp_cycles(5 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(5 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(5 downto g_nr_chans) <= (others => (others => '0'));
gen_latest_timestamp_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
latest_timestamp_cycles(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_latest_timestamp_unused_chans;
--------------------------------------------------------------------------------
-- Then, instantiate the component
cmp_conv_regs : conv_regs
......@@ -969,8 +1042,8 @@ end generate gen_latest_timestamp_unused_chans;
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld,
reg_cr_mpt_o => open,
reg_cr_mpt_wr_o => open,
reg_cr_mpt_o => mpt,
reg_cr_mpt_wr_o => mpt_ld,
reg_ch1pcr_o => ch_pcr(0),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(0)),
......@@ -1060,6 +1133,46 @@ end generate gen_latest_timestamp_unused_chans;
spi_miso_i => flash_miso_i
);
--============================================================================
-- On-board DS18B20 Thermometer logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master : wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
top/conv_common_gw_pkg.vhd
View file @ 3a692ef1
......@@ -43,6 +43,16 @@ use work.genram_pkg.all;
package conv_common_gw_pkg is
--============================================================================
-- Constant declarations
--============================================================================
-- Convenience constant if changes need be made later
--
-- Note that if you change this constant you will make conv-common-gw
-- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
-- _reimplement_ the conv_regs module
constant c_max_nr_chans : natural := 6;
--============================================================================
-- Component declarations
--============================================================================
......@@ -72,10 +82,17 @@ package conv_common_gw_pkg is
g_pgen_gf_len : integer := 4;
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean;
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse counters
g_with_pulse_timetag : boolean;
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
......@@ -166,6 +183,9 @@ package conv_common_gw_pkg is
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
......@@ -494,5 +514,32 @@ package conv_common_gw_pkg is
);
end component conv_ring_buf;
------------------------------------------------------------------------------
-- Manual trigger component
------------------------------------------------------------------------------
component conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- Trigger output, g_pwidth long
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end component conv_man_trig;
end package conv_common_gw_pkg;
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