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conv-common-gw
Commit 08960e47 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in… 

Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in top file conv_common_gw fixed. pulse counters were not resetting after the external loading of new values.
parent 011fbe69
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modules/conv_pulse_gen.vhd
View file @ 08960e47
......@@ -118,7 +118,7 @@ architecture behav of conv_pulse_gen is
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
PRE_IDLE, -- idle state, wait for pulse
CATCH_ERR, -- idle state, wait for pulse
GEN_PULSE_OUTPUT, -- pulse generation
REJ_PULSE_INPUT -- pulse rejection
......@@ -138,7 +138,7 @@ architecture behav of conv_pulse_gen is
-- Rejection time:
-- * Maximum pulse period = g_pperiod*g_pwidth
-- * Allow one cycle to change state from REJ_PULSE_INPUT to PRE_IDLE
-- * Allow one cycle to change state from REJ_PULSE_INPUT to CATCH_ERR
constant c_max_rej : natural := g_pperiod-1;
-- Rising edges result from leading edge of trigger going through a 3 stage synchrnoiser.
......@@ -219,19 +219,17 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i, gf_en_n_i)
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i)
begin
if pulse_out_rst_n = '0' then
pulse_out <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') then --and (gf_en_n_i = '1') then
if (en_i = '1') then
pulse_out <= '1';
end if;
end if;
end process p_pulse_gf_off;
--pulse_gf_on <= '0' when pulse_out_rst_n = '0' else trig_a_i and not gf_en_n_i;
--============================================================================
......@@ -289,7 +287,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
when PRE_IDLE =>
when CATCH_ERR =>
if pulse_cnt >= c_r_edge_sync_delay-1 then
if trig_r_edge_p_i = '1' then
......@@ -298,7 +296,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
else
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
end if;
---------------------------------------------------------------------
......@@ -320,7 +318,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
---------------------------------------------------------------------
when REJ_PULSE_INPUT =>
if pulse_cnt = c_max_rej then
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
else
nxt_state <= REJ_PULSE_INPUT;
end if;
......@@ -334,7 +332,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
-- Generate the FSM logic
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt)
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt, rst_n_i)
begin
case state is
......@@ -350,7 +348,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
pulse_cnt_reset <= '1';
pulse_cnt_clr <= '0';
when PRE_IDLE =>
when CATCH_ERR =>
pulse_out_rst_n <= rst_n_i;
if pulse_cnt < c_r_edge_sync_delay-1 then
pulse_err_p_o <= trig_r_edge_p_i;
......
top/conv_common_gw.vhd
View file @ 08960e47
......@@ -74,8 +74,8 @@ entity conv_common_gw is
g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- output pulse will be limited to period
--For continuous mode operation max freq 4.16kHz
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191;
......@@ -383,9 +383,15 @@ architecture arch of conv_common_gw is
signal fwdg_pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal fwdg_pmisse_bit_rst_ld : std_logic;
signal pmisse_bits_or : std_logic;
--signals for pulse counters
signal rst_ttl_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_blo_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
signal blo_pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt_offset : t_pulse_cnt;
signal blo_pulse_cnt_offset : t_pulse_cnt;
signal ttl_pulse_c : t_pulse_cnt;
signal blo_pulse_c : t_pulse_cnt;
signal ch_ttl_pcr : t_ch_pcr;
......@@ -472,6 +478,7 @@ architecture arch of conv_common_gw is
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0_in : std_logic_vector(7 downto 0);
-- signal TRIG1_in : std_logic_vector(7 downto 0);
-- signal TRIG2_in : std_logic_vector(7 downto 0);
-- signal TRIG3_in : std_logic_vector(7 downto 0);
......@@ -492,26 +499,26 @@ begin
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_20_i,
TRIG0 => TRIG0_in);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_20_i,
-- TRIG0 => TRIG0_in);
chipscope_icon_1 : chipscope_icon
port map ( CONTROL0 => CONTROL);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
TRIG0_in(0) <= pulse_outp_err_sh_p(5);
TRIG0_in(1) <= burst_outp_err_sh_p(5);
-- TRIG0_in(0) <= pulse_outp_err_sh_p(5);
-- TRIG0_in(1) <= burst_outp_err_sh_p(5);
TRIG0_in(2) <= trig_pgen(5);
TRIG0_in(3) <= pulse_outp_sh(5);
-- TRIG0_in(2) <= trig_pgen(5);
-- TRIG0_in(3) <= pulse_outp_sh(5);
TRIG0_in(4) <= pulse_outp_err_lg_p(5);
TRIG0_in(5) <= burst_outp_err_lg_p(5);
TRIG0_in(6) <= pulse_outp_lg(5);
TRIG0_in(7) <= ch_ttl_pcr_ld(5);
-- TRIG0_in(4) <= pulse_outp_err_lg_p(5);
-- TRIG0_in(5) <= burst_outp_err_lg_p(5);
-- TRIG0_in(6) <= pulse_outp_lg(5);
-- TRIG0_in(7) <= ch_ttl_pcr_ld(5);
--============================================================================
......@@ -540,7 +547,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**4)
g_reset_time => 2*(10**6)
)
port map
(
......@@ -629,9 +636,9 @@ gen_no_man_trig : if (g_with_man_trig = false) generate
trig_man <= (others => '0');
end generate gen_no_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Glitch filter
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
......@@ -680,6 +687,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and should have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs : gc_sync_ffs
port map
(
......@@ -691,13 +699,24 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
);
--------------------------------------------------------------------------------
-- Pulse counters:
--------------------------------------------------------------------------------
-- Use Flacter based fast counters to count fast pulses
-- See for more details https://www.doulos.com/knowhow/fpga/fastcounter/
-- The counter below has additional integer output value of the counter plus a
-- reset signal that depends on the system reset in addition to the counter load pulse
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
rst_ttl_cnt(i) <= rst_20 or ch_ttl_pcr_ld(i);
rst_blo_cnt(i) <= rst_20 or ch_blo_pcr_ld(i);
cmp_pulse_cnt_ttl: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
rstcount_i => rst_ttl_cnt(i),
en_i => '1',
trig_i => pulse_ttl_i(i),
count_int_o => ttl_pulse_c(i)
......@@ -706,13 +725,12 @@ cmp_pulse_cnt_ttl: fastevent_counter
cmp_pulse_cnt_blo: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
rstcount_i => rst_blo_cnt(i),
en_i => '1',
trig_i => pulse_blo_i(i),
count_int_o => blo_pulse_c(i)
);
-- First, the pulse counters for the used channels (up to g_nr_chans)
p_pulse_cnt : process (clk_20_i)
......@@ -722,20 +740,15 @@ cmp_pulse_cnt_blo: fastevent_counter
pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt_offset(i) <= (others => '0');
blo_pulse_cnt_offset(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt(i) <= unsigned(ch_ttl_pcr(i));
ttl_pulse_cnt_offset(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt(i) <= unsigned(ch_blo_pcr(i));
blo_pulse_cnt_offset(i) <= unsigned(ch_blo_pcr(i));
else
ttl_pulse_cnt(i) <= ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_c(i);
-- if (trig_chan_redge_p(i) = '1') then
-- pulse_cnt(i) <= pulse_cnt(i) + 1;
-- if (trig_chan_ttl_redge_p(i) = '1') then
-- ttl_pulse_cnt(i) <= ttl_pulse_cnt(i) + 1;
-- elsif (trig_chan_blo_redge_p(i) = '1') then
-- blo_pulse_cnt(i) <= blo_pulse_cnt(i) + 1;
-- end if;
ttl_pulse_cnt(i) <= ttl_pulse_cnt_offset(i)+ ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_cnt_offset(i)+ blo_pulse_c(i);
end if;
end if;
end process p_pulse_cnt;
......
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