urv_cpu.v: add a comment about data memory interface.

56af5885 · Tristan Gingold · 788f6a59 · 56af5885
Commit 56af5885 authored Jan 31, 2019 by Tristan Gingold
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Showing with 10 additions and 8 deletions

urv_cpu.v rtl/urv_cpu.v +10 -8

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--- a/rtl/urv_cpu.v
+++ b/rtl/urv_cpu.v
@@ -50,6 +50,8 @@ module urv_cpu
   input         im_valid_i,
   // data mem I/F
+   // The interface is pipelined: store/load are asserted for one cycle
+   // and then store_done/load_done is awaited.
   output [31:0] dm_addr_o,
   output [31:0] dm_data_s_o,
   input [31:0]  dm_data_l_i,