pmcb: pci core - increased depth of PCI>WB clock crossing fifos

8e5525ae · Dusan Slavinec · 9170fba8 · 8e5525ae
Commit 8e5525ae authored Nov 14, 2017 by Dusan Slavinec
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pci_user_constants.v src/hdl/verilog/pci_user_constants.v +346 -346

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--- a/src/hdl/verilog/pci_user_constants.v
+++ b/src/hdl/verilog/pci_user_constants.v
@@ -99,10 +99,10 @@
 // If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
 // WB_FIFO_RAM_ADDR_LENGTH.
-`define WBW_ADDR_LENGTH 3
+`define WBW_ADDR_LENGTH 8
-`define WBR_ADDR_LENGTH 3
+`define WBR_ADDR_LENGTH 8
-`define PCIW_ADDR_LENGTH 3
+`define PCIW_ADDR_LENGTH 8
-`define PCIR_ADDR_LENGTH 3
+`define PCIR_ADDR_LENGTH 8
 `define FPGA
 //`define XILINX