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hdl-core-lib
mock-turtle
Commits
e7f9469c
Commit
e7f9469c
authored
Mar 20, 2018
by
Dimitris Lampridis
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hdl: proposed fix for svec_mt_demo to prevent gpio pins from being trimmed away during synthesis
parent
a5b855ca
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3 changed files
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30 additions
and
26 deletions
+30
-26
general-cores
hdl/ip_cores/general-cores
+1
-1
svec_mt_demo.ucf
hdl/syn/svec_mt_demo/svec_mt_demo.ucf
+8
-11
svec_mt_demo.vhd
hdl/top/svec_mt_demo/svec_mt_demo.vhd
+21
-14
No files found.
general-cores
@
e5e006a4
Subproject commit
61ca3f49b61233e922f4c2c034e1b62728c124bf
Subproject commit
e5e006a435da38ab636fe63dd9475ee9847e1c46
hdl/syn/svec_mt_demo/svec_mt_demo.ucf
View file @
e7f9469c
...
...
@@ -256,17 +256,14 @@ NET "fp_gpio2_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio34_a2b_o" LOC=V28;
NET "fp_gpio34_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio1_b" LOC=R30;
NET "fp_gpio1_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio2_b" LOC=T28;
NET "fp_gpio2_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio3_b" LOC=U29;
NET "fp_gpio3_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio4_b" LOC=V27;
NET "fp_gpio4_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[0]" LOC=R30;
NET "fp_gpio_in[0]" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[1]" LOC=T28;
NET "fp_gpio_in[1]" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[2]" LOC=U29;
NET "fp_gpio_in[2]" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[3]" LOC=V27;
NET "fp_gpio_in[3]" IOSTANDARD="LVCMOS33";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
...
...
hdl/top/svec_mt_demo/svec_mt_demo.vhd
View file @
e7f9469c
...
...
@@ -59,10 +59,7 @@ entity svec_mt_demo is
fp_gpio1_a2b_o
:
out
std_logic
;
fp_gpio2_a2b_o
:
out
std_logic
;
fp_gpio34_a2b_o
:
out
std_logic
;
fp_gpio1_b
:
inout
std_logic
;
fp_gpio2_b
:
inout
std_logic
;
fp_gpio3_b
:
inout
std_logic
;
fp_gpio4_b
:
inout
std_logic
;
fp_gpio_b
:
inout
std_logic_vector
(
3
downto
0
);
-- Bypass VME core, useful only in simulation
-- synthesis translate_off
...
...
@@ -192,6 +189,11 @@ architecture arch of svec_mt_demo is
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_locked
:
std_logic
;
signal
fp_gpio_in
:
std_logic_vector
(
3
downto
0
);
attribute
keep
:
string
;
attribute
keep
of
fp_gpio_in
:
signal
is
"true"
;
begin
-- architecture arch
U_Buf_CLK_PLL
:
IBUFGDS
...
...
@@ -363,6 +365,7 @@ begin -- architecture arch
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_pins
=>
24
,
g_with_builtin_sync
=>
FALSE
,
g_with_builtin_tristates
=>
FALSE
)
port
map
(
clk_sys_i
=>
clk_sys
,
...
...
@@ -378,6 +381,7 @@ begin -- architecture arch
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_pins
=>
24
,
g_with_builtin_sync
=>
FALSE
,
g_with_builtin_tristates
=>
FALSE
)
port
map
(
clk_sys_i
=>
clk_sys
,
...
...
@@ -397,16 +401,19 @@ begin -- architecture arch
fp_gpio34_a2b_o
<=
cpu_gpio_oen
(
2
);
-- FP GPIO bidir in/out (3 and 4 share the same direction line)
fp_gpio1_b
<=
cpu_gpio_out
(
0
)
when
cpu_gpio_oen
(
0
)
=
'1'
else
'Z'
;
fp_gpio2_b
<=
cpu_gpio_out
(
1
)
when
cpu_gpio_oen
(
1
)
=
'1'
else
'Z'
;
fp_gpio3_b
<=
cpu_gpio_out
(
2
)
when
cpu_gpio_oen
(
2
)
=
'1'
else
'Z'
;
fp_gpio4_b
<=
cpu_gpio_out
(
3
)
when
cpu_gpio_oen
(
2
)
=
'1'
else
'Z'
;
-- gpio inputs (same for both CPUs)
cpu_gpio_in
(
0
)
<=
fp_gpio1_b
;
cpu_gpio_in
(
1
)
<=
fp_gpio2_b
;
cpu_gpio_in
(
2
)
<=
fp_gpio3_b
;
cpu_gpio_in
(
3
)
<=
fp_gpio4_b
;
fp_gpio_gen
:
for
i
in
0
to
3
generate
fp_gpio_b
(
i
)
<=
cpu_gpio_out
(
i
)
when
cpu_gpio_oen
(
i
)
=
'1'
else
'Z'
;
fp_gpio_in
(
i
)
<=
fp_gpio_b
(
i
);
gpio_sync_ffs
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys
,
rst_n_i
=>
rst_n_sys
,
data_i
=>
fp_gpio_in
(
i
),
synced_o
=>
cpu_gpio_in
(
i
));
end
generate
fp_gpio_gen
;
cpu_gpio_in
(
23
downto
4
)
<=
cpu_gpio_out
(
23
downto
4
);
...
...
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