External/aux clock generics
Not all settings of g_with_external_clock_input and g_aux_clks
work.
In particular, the default works:
g_with_external_clock_input : boolean := true;
g_aux_clks : integer := 0;
this configuration
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
gives the following error:
ERROR:HDLCompiler:533 -
"X:\FPGA\Visual\Frequency_Program_WR_Svec\SVEC_VISUAL2014\SVEC_VISUAL_GEN_PTPV3.vhd"
Line 38618: Index 3 is out of array constraint 2 downto 0 for target
tags_p
Netlist
wr_softpll_ng(22,1,2,false,false,false,true,125000000,10000000,pipelined,byte)(rtl)
remains a blackbox, due to errors in its contents