1 clock cycle glitch on link_ok_o WRPC output
Such glitch was happening in the WR Endpoint module (and from there was
propagated to the WRPC output port). After the autonegotation FSM was in
pseudo AN_ENABLED state caused by synced=LOW (in this state, link_ok
is HIGH). When synced goes HIGH, the FSM enters "proper" AN_ENABLED
state, it drives link_ok LOW.
This glitch can cause problems to user-defined HDL modules that e.g.
want to block outgoing user traffic when the link is not ready.
The fix was done in commit:
043c0d3e: [PCS bugfix] remove a 1-cyc glitch from link_ok_o signal