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White Rabbit core collection
Commit f5f7f210 authored by Peter Jansweijer's avatar Peter Jansweijer
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prepaired BMM files for MMI creation (added ram block address range) 

added BMM_INFO_DESIGN property to XDC
parent 63edfdae
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Showing with 98 additions and 94 deletions
top/spec7_ref_design/spec7_wr_ref_top.bmm
View file @ f5f7f210
/* FILE : clbv3_wr_ref_top.bmm /* FILE : spec7_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory. * Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file * ISE: Run Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1 * attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!* * VIVADO: find brams (see also viv_find_brams.tcl)
* set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]
* foreach ram_block $my_rams {
* puts $ram_block
* }
* Note: *THE RAMLOOP ORDER WITHIN A BUS BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory * Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop * content will be swapped and the program fails to execute. Apparently the ramloop
* number and bit definitions are not read by data2mem. * number and bit definitions are not read by data2mem.
* *
*
* Address space LM32 memory * Address space LM32 memory
* g_dpram_size = 90112/4 = 22528 * g_dpram_size = 128 KB = 131072 bytes / 4 = 32768 32-bit words
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
* *
* ATTENTION PARITY! * ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as * Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is * RAMB32 (instead of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction * defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled * in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data. * such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command * Note that this can be examined using the data2mem command
* "data2mem -bm clbv3_wr_ref_top_bd.bmm -bt clbv3_wr_ref_top_elf.bit -d > dump.txt" * "data2mem -bm spec7_wr_ref_top_bd.bmm -bt spec7_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
* *
****************************************************************************************/ ****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF] ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32 ADDRESS_RANGE RAMB32
BUS_BLOCK BUS_BLOCK
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31:31] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30:30] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29:29] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28:28] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27:27] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26:26] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25:25] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24:24] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23:23] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22:22] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21:21] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20:20] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19:19] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18:18] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17:17] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16:16] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15:15] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14:14] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13:13] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12:12] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11:11] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10:10] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9:9] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8:8] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7:7] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6:6] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5:5] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4:4] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3:3] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2:2] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1:1] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0:0] [0:32767];
END_BUS_BLOCK; END_BUS_BLOCK;
END_ADDRESS_RANGE; END_ADDRESS_RANGE;
END_ADDRESS_SPACE; END_ADDRESS_SPACE;
\ No newline at end of file
top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ f5f7f210
...@@ -22,7 +22,7 @@ set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i] ...@@ -22,7 +22,7 @@ set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i] create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i] create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
# Set divide by 2 propety for generated clk_dmtd (platform xilinx: g_direct_dmtd = TRUE) # Set divide by 2 property for generated clk_dmtd (platform xilinx: g_direct_dmtd = TRUE)
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q] create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (platform xilinx: g_direct_dmtd = TRUE) # Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (platform xilinx: g_direct_dmtd = TRUE)
...@@ -43,6 +43,9 @@ set_clock_groups -asynchronous \ ...@@ -43,6 +43,9 @@ set_clock_groups -asynchronous \
-group dio_clk \ -group dio_clk \
-group clk_ext_mul -group clk_ext_mul
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
set_property BMM_INFO_DESIGN spec7_wr_ref_top_bd.bmm [current_design]
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
# -- SPI interface to DACs # -- SPI interface to DACs
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
......
top/spec7_write_design/spec7_write_top.bmm
View file @ f5f7f210
/* FILE : clbv3_wr_ref_top.bmm /* FILE : spec7_write_top.bmm
* Define a BRAM map for the LM32 memory. * Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file * ISE: Run Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1 * attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!* * VIVADO: find brams (see also viv_find_brams.tcl)
* set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]
* foreach ram_block $my_rams {
* puts $ram_block
* }
* Note: *THE RAMLOOP ORDER WITHIN A BUS BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory * Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop * content will be swapped and the program fails to execute. Apparently the ramloop
* number and bit definitions are not read by data2mem. * number and bit definitions are not read by data2mem.
* *
*
* Address space LM32 memory * Address space LM32 memory
* g_dpram_size = 90112/4 = 22528 * g_dpram_size = 128 KB = 131072 bytes / 4 = 32768 32-bit words
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
* *
* ATTENTION PARITY! * ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as * Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is * RAMB32 (instead of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction * defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled * in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data. * such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command * Note that this can be examined using the data2mem command
* "data2mem -bm clbv3_wr_ref_top_bd.bmm -bt clbv3_wr_ref_top_elf.bit -d > dump.txt" * "data2mem -bm spec7_write_top_bd.bmm -bt spec7_write_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
* *
****************************************************************************************/ ****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF] ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32 ADDRESS_RANGE RAMB32
BUS_BLOCK BUS_BLOCK
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31:31] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30:30] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29:29] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28:28] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27:27] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26:26] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25:25] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24:24] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23:23] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22:22] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21:21] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20:20] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19:19] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18:18] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17:17] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16:16] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15:15] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14:14] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13:13] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12:12] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11:11] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10:10] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9:9] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8:8] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7:7] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6:6] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5:5] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4:4] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3:3] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2:2] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1:1] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0]; cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0:0] [0:32767];
END_BUS_BLOCK; END_BUS_BLOCK;
END_ADDRESS_RANGE; END_ADDRESS_RANGE;
END_ADDRESS_SPACE; END_ADDRESS_SPACE;
\ No newline at end of file
top/spec7_write_design/spec7_write_top.xdc
View file @ f5f7f210
...@@ -22,7 +22,7 @@ set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i] ...@@ -22,7 +22,7 @@ set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i] create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i] create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
# Set divide by 2 propety for generated clk_dmtd (platform xilinx: g_direct_dmtd = TRUE) # Set divide by 2 property for generated clk_dmtd (platform xilinx: g_direct_dmtd = TRUE)
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q] create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (platform xilinx: g_direct_dmtd = TRUE) # Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (platform xilinx: g_direct_dmtd = TRUE)
...@@ -50,6 +50,9 @@ set_clock_groups -asynchronous \ ...@@ -50,6 +50,9 @@ set_clock_groups -asynchronous \
set_multicycle_path 8 -setup -from [get_clocks "*TXOUTCLK*"] -to [get_clocks "*clk_500m*"] set_multicycle_path 8 -setup -from [get_clocks "*TXOUTCLK*"] -to [get_clocks "*clk_500m*"]
set_multicycle_path 7 -hold -from [get_clocks "*TXOUTCLK*"] -to [get_clocks "*clk_500m*"] set_multicycle_path 7 -hold -from [get_clocks "*TXOUTCLK*"] -to [get_clocks "*clk_500m*"]
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
set_property BMM_INFO_DESIGN spec7_write_top_bd.bmm [current_design]
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
# -- SPI interface to DACs # -- SPI interface to DACs
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
......
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