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f1a2fe27
Commit
f1a2fe27
authored
Aug 17, 2020
by
Grzegorz Daniluk
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adding BSP for PXIe-FMC board with Xilinx ZU7
parent
57c9e69e
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9 changed files
with
856 additions
and
1 deletion
+856
-1
Manifest.py
board/Manifest.py
+1
-1
Manifest.py
board/pxie-fmc/Manifest.py
+10
-0
wr_pxie_fmc_pkg.vhd
board/pxie-fmc/wr_pxie_fmc_pkg.vhd
+118
-0
xwrc_board_pxie_fmc.vhd
board/pxie-fmc/xwrc_board_pxie_fmc.vhd
+369
-0
Manifest.py
syn/pxie_fmc_ref_design/Manifest.py
+22
-0
pxie_fmc.tcl
syn/pxie_fmc_ref_design/pxie_fmc.tcl
+52
-0
pxie_fmc_ref_design.xdc
syn/pxie_fmc_ref_design/pxie_fmc_ref_design.xdc
+80
-0
Manifest.py
top/pxie_fmc_ref_design/Manifest.py
+14
-0
pxie_fmc_ref_top.vhd
top/pxie_fmc_ref_design/pxie_fmc_ref_top.vhd
+190
-0
No files found.
board/Manifest.py
View file @
f1a2fe27
try
:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"clbv2"
,
"clbv3"
,
"clbv4"
,
"common"
]:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"clbv2"
,
"clbv3"
,
"clbv4"
,
"
pxie-fmc"
,
"
common"
]:
modules
=
{
"local"
:
[
board
]
}
except
NameError
:
pass
board/pxie-fmc/Manifest.py
0 → 100644
View file @
f1a2fe27
files
=
[
"wr_pxie_fmc_pkg.vhd"
,
"xwrc_board_pxie_fmc.vhd"
,
]
modules
=
{
"local"
:
[
"../common"
,
]
}
board/pxie-fmc/wr_pxie_fmc_pkg.vhd
0 → 100644
View file @
f1a2fe27
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for SPEC package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_pxie_fmc_pkg.vhd
-- Author(s) : Greg Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
streamers_pkg
.
all
;
package
wr_pxie_fmc_pkg
is
component
xwrc_board_pxie_fmc
is
generic
(
g_simulation
:
integer
:
=
0
;
g_aux_clks
:
integer
:
=
0
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
);
port
(
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
wr_clk_helper_125m_p_i
:
in
std_logic
;
wr_clk_helper_125m_n_i
:
in
std_logic
;
wr_clk_main_125m_p_i
:
in
std_logic
;
wr_clk_main_125m_n_i
:
in
std_logic
;
wr_clk_sfp_125m_p_i
:
in
std_logic
;
wr_clk_sfp_125m_n_i
:
in
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
aux_master_o
:
out
t_wishbone_master_out
;
aux_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_pxie_fmc
;
end
wr_pxie_fmc_pkg
;
board/pxie-fmc/xwrc_board_pxie_fmc.vhd
0 → 100644
View file @
f1a2fe27
This diff is collapsed.
Click to expand it.
syn/pxie_fmc_ref_design/Manifest.py
0 → 100644
View file @
f1a2fe27
board
=
"pxie-fmc"
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xczu7cg"
syn_grade
=
"-1"
syn_package
=
"ffvf1517"
syn_top
=
"pxie_fmc_ref_top"
syn_project
=
"pxie_fmc_ref_top"
syn_tool
=
"vivado"
files
=
[
"pxie_fmc_ref_design.xdc"
,
]
modules
=
{
"local"
:
[
"../../top/pxie_fmc_ref_design/"
,
],
}
syn/pxie_fmc_ref_design/pxie_fmc.tcl
0 → 100644
View file @
f1a2fe27
set
projDir
[
file
dirname
[
info
script
]]
set_param general.maxThreads 8
get_param general.maxThreads
# Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
set
speed 1
set
fpga xczu7cg-ffvf1517-$
{
speed
}
-e
set
device
${fpga}
set
top pxie_fmc_ref_top
# Check hdlmake has generated file dependencies
if
{
!
[
file
exists files.tcl
]}
{
puts
"File: files.tcl not found, please check hdlmake has generated the file dependencies."
exit 1
}
source
files.tcl
# constraint files
read_xdc
$proj
Dir/pxie_fmc_ref_design.xdc
set
start_time
[
clock
seconds
]
synth_design -top
${top}
-part
${device}
>
${top}
_synth.log
write_checkpoint -force
${top}
_synth
opt_design -directive Explore -verbose >
${top}
_opt.log
write_checkpoint -force
${top}
_opt
place_design -directive Explore >
${top}
_place.log
write_checkpoint -force
${projDir}
/$
{
top
}
_place
phys_opt_design -directive Explore >
${top}
_phys_opt.log
write_checkpoint -force
${projDir}
/$
{
top
}
_phys_opt
route_design -directive Explore >
${top}
_route.log
write_checkpoint -force
${projDir}
/$
{
top
}
_route
report_timing_summary -file
${top}
_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type full -file
${top}
_timing.rpt
report_utilization -hierarchical -file
${top}
_utilization.rpt
report_io -file
${top}
_pin.rpt
# bitstream configuration...
write_bitstream -force
${projDir}
/$
{
top
}
.bit
set
end_time
[
clock
seconds
]
set
total_time
[
expr
{
$end
_time -
$start
_time
}
]
set
absolute_time
[
clock
format
$total
_time -format
{
%H:%M:%S
}
-gmt true
]
puts
"
\n
total build time:
$absolute
_time
\n
"
syn/pxie_fmc_ref_design/pxie_fmc_ref_design.xdc
0 → 100644
View file @
f1a2fe27
##################
# Clocks
##################
create_clock -period 8.000 -name wr_clk_helper_125m -waveform {0.000 4.000} [get_ports {wr_clk_helper_125m_p_i}]
create_clock -period 8.000 -name wr_clk_main_125m -waveform {0.000 4.000} [get_ports {wr_clk_main_125m_p_i}]
create_clock -period 8.000 -name wr_clk_sfp_125m -waveform {0.000 4.000} [get_ports {wr_clk_sfp_125m_p_i}]
create_clock -period 16.000 -name gth_txclk -waveform {0.000 8.000} [get_nets cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/tx_out_clk_o]
create_clock -period 16.000 -name gth_rxclk -waveform {0.000 8.000} [get_nets cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/rx_rbclk_o]
create_generated_clock -name clk_dmtd -source [get_ports {wr_clk_helper_125m_p_i}] -divide_by 2 [get_pins cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_default_plls.gen_zynqus_default_plls.cmp_clk_dmtd_buf_o/O]
set_clock_groups -asynchronous -group {wr_clk_main_125m wr_clk_sfp_125m} -group {wr_clk_helper_125m clk_dmtd} -group {gth_txclk} -group {gth_rxclk}
##################
# I/O constraints
##################
set_property PACKAGE_PIN AU9 [get_ports {user_led_o[0]}]
set_property PACKAGE_PIN AW9 [get_ports {user_led_o[1]}]
set_property PACKAGE_PIN AV9 [get_ports {user_led_o[2]}]
set_property PACKAGE_PIN AW10 [get_ports eeprom_scl_b]
set_property PACKAGE_PIN AW11 [get_ports eeprom_sda_b]
set_property PACKAGE_PIN K14 [get_ports pll25dac_cs_n_o]
set_property PACKAGE_PIN L12 [get_ports pll20dac_cs_n_o]
set_property PACKAGE_PIN K13 [get_ports plldac_din_o]
set_property PACKAGE_PIN J14 [get_ports plldac_sclk_o]
set_property PACKAGE_PIN A11 [get_ports pps_p_o]
set_property PACKAGE_PIN K12 [get_ports ps_por_i]
set_property PACKAGE_PIN G10 [get_ports sfp_det_i]
set_property PACKAGE_PIN K10 [get_ports sfp_los_i]
set_property PACKAGE_PIN AM2 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN AH10 [get_ports wr_clk_sfp_125m_p_i]
set_property PACKAGE_PIN AU21 [get_ports sfp_scl_b]
set_property PACKAGE_PIN AT21 [get_ports sfp_sda_b]
set_property PACKAGE_PIN D12 [get_ports sfp_tx_disable_o]
set_property PACKAGE_PIN C12 [get_ports uart_txd_o]
set_property PACKAGE_PIN C14 [get_ports uart_rxd_i]
set_property PACKAGE_PIN AP20 [get_ports wr_clk_helper_125m_p_i]
set_property PACKAGE_PIN AN19 [get_ports wr_clk_main_125m_p_i]
set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda_b]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl_b]
set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports pps_p_o]
set_property IOSTANDARD LVCMOS33 [get_ports ps_por_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_det_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd_i]
set_property IOSTANDARD LVDS [get_ports wr_clk_helper_125m_p_i]
set_property IOSTANDARD LVDS [get_ports wr_clk_main_125m_p_i]
set_property OFFCHIP_TERM NONE [get_ports eeprom_scl_b]
set_property OFFCHIP_TERM NONE [get_ports eeprom_sda_b]
set_property OFFCHIP_TERM NONE [get_ports pll20dac_cs_n_o]
set_property OFFCHIP_TERM NONE [get_ports pll25dac_cs_n_o]
set_property OFFCHIP_TERM NONE [get_ports plldac_din_o]
set_property OFFCHIP_TERM NONE [get_ports plldac_sclk_o]
set_property OFFCHIP_TERM NONE [get_ports pps_p_o]
set_property OFFCHIP_TERM NONE [get_ports sfp_scl_b]
set_property OFFCHIP_TERM NONE [get_ports sfp_sda_b]
set_property OFFCHIP_TERM NONE [get_ports sfp_tx_disable_o]
set_property OFFCHIP_TERM NONE [get_ports uart_txd_o]
set_property OFFCHIP_TERM NONE [get_ports user_led_o[2]]
set_property OFFCHIP_TERM NONE [get_ports user_led_o[1]]
set_property OFFCHIP_TERM NONE [get_ports user_led_o[0]]
#revert back to original instance
current_instance -quiet
top/pxie_fmc_ref_design/Manifest.py
0 → 100644
View file @
f1a2fe27
fetchto
=
"../../ip_cores"
files
=
[
"pxie_fmc_ref_top.vhd"
,
]
modules
=
{
"local"
:
[
"../../"
,
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git"
,
"git://ohwr.org/hdl-core-lib/etherbone-core.git"
,
],
}
top/pxie_fmc_ref_design/pxie_fmc_ref_top.vhd
0 → 100644
View file @
f1a2fe27
-------------------------------------------------------------------------------
-- Title : WRPC reference design for PXIe-FMC board
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : pxie_fmc_ref_top.vhd
-- Author(s) : Greg Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the PXIe-FMC
-- board.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a PXIe-FMC board.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-- PXIe-FMC: https://ohwr.org/project/pxie-fmc
--
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gn4124_core_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_pxie_fmc_pkg
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
pxie_fmc_ref_top
is
generic
(
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
ps_por_i
:
in
std_logic
;
wr_clk_helper_125m_p_i
:
in
std_logic
;
wr_clk_helper_125m_n_i
:
in
std_logic
;
wr_clk_main_125m_p_i
:
in
std_logic
;
wr_clk_main_125m_n_i
:
in
std_logic
;
wr_clk_sfp_125m_p_i
:
in
std_logic
;
wr_clk_sfp_125m_n_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SFP I/Os for transceiver
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
;
sfp_sda_b
:
inout
std_logic
;
sfp_scl_b
:
inout
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- EEPROM I2C interface for storing configuration and accessing unique ID
---------------------------------------------------------------------------
eeprom_sda_b
:
inout
std_logic
;
eeprom_scl_b
:
inout
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- LEDs
---------------------------------------------------------------------------
user_led_o
:
out
std_logic_vector
(
2
downto
0
);
pps_p_o
:
out
std_logic
);
end
entity
pxie_fmc_ref_top
;
architecture
top
of
pxie_fmc_ref_top
is
signal
rst_n
:
std_logic
;
signal
clk_sys_62m5
:
std_logic
;
signal
sfp_scl_out
,
sfp_scl_in
:
std_logic
;
signal
sfp_sda_out
,
sfp_sda_in
:
std_logic
;
signal
eeprom_scl_out
,
eeprom_scl_in
:
std_logic
;
signal
eeprom_sda_out
,
eeprom_sda_in
:
std_logic
;
begin
-- do not use PS_POR for now
rst_n
<=
'1'
;
--not ps_por_i;
user_led_o
(
2
)
<=
'1'
;
cmp_xwrc_board_pxie_fmc
:
xwrc_board_pxie_fmc
generic
map
(
g_simulation
=>
g_SIMULATION
,
g_dpram_initf
=>
"../../bin/wrpc/wrc_pxie.bram"
)
port
map
(
areset_n_i
=>
rst_n
,
wr_clk_helper_125m_p_i
=>
wr_clk_helper_125m_p_i
,
wr_clk_helper_125m_n_i
=>
wr_clk_helper_125m_n_i
,
wr_clk_main_125m_p_i
=>
wr_clk_main_125m_p_i
,
wr_clk_main_125m_n_i
=>
wr_clk_main_125m_n_i
,
wr_clk_sfp_125m_p_i
=>
wr_clk_sfp_125m_p_i
,
wr_clk_sfp_125m_n_i
=>
wr_clk_sfp_125m_n_i
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_din_o
=>
plldac_din_o
,
pll25dac_cs_n_o
=>
pll25dac_cs_n_o
,
pll20dac_cs_n_o
=>
pll20dac_cs_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_i
=>
sfp_sda_in
,
sfp_sda_o
=>
sfp_sda_out
,
sfp_scl_i
=>
sfp_scl_in
,
sfp_scl_o
=>
sfp_scl_out
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_in
,
eeprom_sda_o
=>
eeprom_sda_out
,
eeprom_scl_i
=>
eeprom_scl_in
,
eeprom_scl_o
=>
eeprom_scl_out
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
led_act_o
=>
user_led_o
(
0
),
led_link_o
=>
user_led_o
(
1
),
pps_p_o
=>
pps_p_o
);
sfp_scl_b
<=
'0'
when
sfp_scl_out
=
'0'
else
'Z'
;
sfp_sda_b
<=
'0'
when
sfp_sda_out
=
'0'
else
'Z'
;
sfp_scl_in
<=
sfp_scl_b
;
sfp_sda_in
<=
sfp_sda_b
;
eeprom_scl_b
<=
'0'
when
eeprom_scl_out
=
'0'
else
'Z'
;
eeprom_sda_b
<=
'0'
when
eeprom_sda_out
=
'0'
else
'Z'
;
eeprom_scl_in
<=
eeprom_scl_b
;
eeprom_sda_in
<=
eeprom_sda_b
;
end
top
;
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