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White Rabbit core collection
Commit dedbf241 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address… 

wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)
parent 28191b5a
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        Showing with 31 additions and 7 deletions
        modules/wrc_core/wr_core.vhd
        View file @ dedbf241
        ......@@ -6,7 +6,7 @@
        -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
        -- Company : CERN (BE-CO-HT)
        -- Created : 2011-02-02
        -- Last update: 2020-08-19
        -- Last update: 2020-11-02
        -- Platform : FPGA-generics
        -- Standard : VHDL
        -------------------------------------------------------------------------------
        ......@@ -76,8 +76,9 @@ entity wr_core is
        g_simulation : integer := 0;
        -- set to false to reduce the number of information printed during simulation
        g_verbose : boolean := true;
        g_with_external_clock_input : boolean := true;
        --
        g_with_external_clock_input : boolean := true;
        g_ram_address_space_size_kb : integer := 128;
        --
        g_board_name : string := "NA ";
        g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
        g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
        ......@@ -451,13 +452,31 @@ architecture struct of wr_core is
        signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
        signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
        impure function f_pick_secbar_base return std_logic_vector is
        begin
        if g_ram_address_space_size_kb = 128 then
        return x"00020000";
        else
        return x"00040000";
        end if;
        end f_pick_secbar_base;
        impure function f_pick_sdb_base return std_logic_vector is
        begin
        if g_ram_address_space_size_kb = 128 then
        return x"00030000";
        else
        return x"00050000";
        end if;
        end f_pick_sdb_base;
        -----------------------------------------------------------------------------
        --WB intercon
        -----------------------------------------------------------------------------
        constant c_layout : t_sdb_record_array(1 downto 0) :=
        (0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
        1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00040000"));
        constant c_sdb_address : t_wishbone_address := x"00050000";
        1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, f_pick_secbar_base));
        constant c_sdb_address : t_wishbone_address := f_pick_sdb_base;
        signal cbar_slave_i : t_wishbone_slave_in_array (2 downto 0);
        signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
        ......
        modules/wrc_core/wrcore_pkg.vhd
        View file @ dedbf241
        ......@@ -6,7 +6,7 @@
        -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
        -- Company : CERN (BE-CO-HT)
        -- Created : 2011-05-11
        -- Last update: 2020-08-19
        -- Last update: 2020-11-02
        -- Platform : FPGA-generics
        -- Standard : VHDL
        -------------------------------------------------------------------------------
        ......@@ -367,6 +367,7 @@ package wrcore_pkg is
        generic(
        g_simulation : integer := 0;
        g_verbose : boolean := true;
        g_ram_address_space_size_kb : integer := 128;
        g_board_name : string := "NA ";
        g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
        g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
        ......@@ -520,6 +521,7 @@ package wrcore_pkg is
        --up simulation
        g_simulation : integer := 0;
        g_verbose : boolean := true;
        g_ram_address_space_size_kb : integer := 128;
        g_with_external_clock_input : boolean := true;
        --
        g_board_name : string := "NA ";
        ......
        modules/wrc_core/xwr_core.vhd
        View file @ dedbf241
        ......@@ -6,7 +6,7 @@
        -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
        -- Company : CERN (BE-CO-HT)
        -- Created : 2011-02-02
        -- Last update: 2020-08-19
        -- Last update: 2020-11-02
        -- Platform : FPGA-generics
        -- Standard : VHDL
        -------------------------------------------------------------------------------
        ......@@ -76,6 +76,8 @@ entity xwr_core is
        -- set to false to reduce the number of information printed during simulation
        g_verbose : boolean := true;
        g_with_external_clock_input : boolean := true;
        g_ram_address_space_size_kb : integer := 128;
        --
        g_board_name : string := "NA ";
        g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
        ......@@ -286,6 +288,7 @@ begin
        generic map(
        g_simulation => g_simulation,
        g_verbose => g_verbose,
        g_ram_address_space_size_kb => g_ram_address_space_size_kb,
        g_board_name => g_board_name,
        g_flash_secsz_kb => g_flash_secsz_kb,
        g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
        ......
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