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White Rabbit core collection
Commit 20e019e0 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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adding ISE/Quartus project files for v4.0 release

parent 707fcfce
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syn/spec_ref_design/Makefile
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...@@ -59,329 +59,348 @@ endif ...@@ -59,329 +59,348 @@ endif
CWD := $(shell pwd) CWD := $(shell pwd)
FILES := ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../modules/wr_pps_gen/wr_pps_gen.vhd \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd \
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \ ../../modules/wr_dacs/spec_serial_dac_arb.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
../../modules/wr_tbi_phy/dec_8b10b.vhd \
../../modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../modules/wr_endpoint/ep_wishbone_controller.vhd \ ../../modules/wr_endpoint/ep_wishbone_controller.vhd \
../../modules/wr_endpoint/endpoint_pkg.vhd \
../../modules/wr_tbi_phy/enc_8b10b.vhd \
../../modules/wrc_core/wrc_syscon_pkg.vhd \
../../modules/wr_eca/eca_tlu_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../platform/xilinx/chipscope/chipscope_icon.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../modules/wr_eca/eca_free.vhd \ ../../modules/wr_eca/eca_free.vhd \
../../modules/wr_endpoint/ep_rtu_header_extract.vhd \ ../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \
../../modules/wr_eca/eca_msi.vhd \
../../modules/wr_endpoint/wr_endpoint.vhd \
run.tcl \
../../modules/wr_tlu/tlu_fsm.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../modules/wr_eca/eca_ac_wbm_auto.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../board/spec/xwrc_board_spec.vhd \
spec_wr_ref.xise \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../modules/wr_endpoint/endpoint_pkg.vhd \
../../modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd \
../../modules/wr_eca/eca_wb_event.vhd \
../../modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../modules/wr_tlu/tlu.vhd \
../../modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../modules/wr_streamers/rx_streamer.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
../../modules/wr_endpoint/ep_autonegotiation.vhd \
../../board/common/xwrc_board_common.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../modules/wr_eca/eca_queue.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/wr_streamers/gc_escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../modules/wrc_core/wb_reset.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../top/spec_ref_design/spec_wr_ref_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../modules/wr_endpoint/ep_leds_controller.vhd \
../../modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
../../modules/wr_tbi_phy/dec_8b10b.vhd \
../../modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../modules/wr_endpoint/ep_tx_path.vhd \ ../../modules/wr_endpoint/ep_tx_path.vhd \
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \ ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \ ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../modules/wrc_core/wrc_periph.vhd \ ../../modules/wrc_core/wrc_periph.vhd \
../../modules/wr_eca/eca_pkg.vhd \ ../../modules/wr_eca/eca_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../board/spec/wr_spec_pkg.vhd \ ../../board/spec/wr_spec_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \ ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \ ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../modules/wr_eca/eca_msi.vhd \
../../modules/wrc_core/wr_core.vhd \ ../../modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../modules/wr_mini_nic/xwr_mini_nic.vhd \
../../modules/timing/hpll_period_detect.vhd \
../../modules/wr_endpoint/ep_tx_header_processor.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \ ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \ ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../modules/wr_eca/eca_channel.vhd \
../../modules/wr_eca/wr_eca.vhd \
../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../modules/wr_eca/eca_offset.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \ ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../modules/wr_endpoint/ep_crc32_pkg.vhd \
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../modules/wr_eca/eca_wb_event.vhd \
../../modules/wr_tlu/tlu_fsm.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \ ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \ ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../modules/wr_dacs/spec_serial_dac_arb.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../modules/wr_eca/eca_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \ ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \ ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../modules/wr_streamers/wr_transmission_wb.vhd \ ../../modules/wr_streamers/wr_transmission_wb.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../modules/wr_tlu/tlu_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_eca/eca_ac_wbm_auto.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \ ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../board/spec/xwrc_board_spec.vhd \
../../modules/wr_eca/eca_tlu.vhd \
../../modules/wrc_core/xwr_syscon_wb.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \ ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \ ../../modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../platform/xilinx/wr_xilinx_pkg.vhd \ ../../platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd \
../../modules/fabric/wr_fabric_pkg.vhd \
../../modules/wr_eca/eca_sdp.vhd \
../../modules/wr_eca/eca_scan.vhd \
../../modules/wr_streamers/xrtx_streamers_stats.vhd \
../../modules/wr_endpoint/ep_rx_path.vhd \ ../../modules/wr_endpoint/ep_rx_path.vhd \
../../modules/wr_streamers/dropping_buffer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \ ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../modules/fabric/xwrf_reg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \ ../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
../../modules/timing/dmtd_phase_meas.vhd \ ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \ ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/wr_eca/eca_scubus_channel.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../modules/timing/pulse_stamper.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \ ../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
../../modules/wr_streamers/rx_streamer.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd \
../../modules/timing/dmtd_with_deglitcher.vhd \ ../../modules/fabric/xwb_fabric_sink.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \ ../../modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../modules/wrc_core/wrc_syscon_wb.vhd \
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../modules/wr_eca/eca.vhd \
../../modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../modules/wr_softpll_ng/spll_period_detect.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../modules/wr_eca/eca_ac_wbm.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../modules/timing/pulse_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \ ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
../../modules/wr_eca/eca_search.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../modules/wr_tlu/tlu_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../modules/timing/multi_dmtd_with_deglitcher.vhd \
../../modules/wr_endpoint/ep_tx_header_processor.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../modules/wr_eca/eca_channel.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../modules/wr_eca/eca_auto.vhd \
../../modules/wr_eca/eca_tlu.vhd \
../../modules/wrc_core/xwr_syscon_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../modules/wr_streamers/xrtx_streamers_stats.vhd \
../../modules/fabric/xwrf_reg.vhd \
../../modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../platform/xilinx/xwrc_platform_xilinx.vhd \ ../../platform/xilinx/xwrc_platform_xilinx.vhd \
../../modules/wr_endpoint/ep_timestamping_unit.vhd \ ../../modules/wr_endpoint/ep_timestamping_unit.vhd \
../../modules/fabric/xwb_fabric_sink.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \ ../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \ ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../modules/wrc_core/wrcore_pkg.vhd \
../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../modules/wr_eca/eca_adder.vhd \ ../../modules/wr_eca/eca_adder.vhd \
run.tcl \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../modules/fabric/xwrf_mux.vhd \ ../../modules/wrc_core/xwr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../modules/wr_tlu/tlu.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \ ../../modules/wr_eca/eca_piso_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../modules/wrc_core/wrc_syscon_wb.vhd \
../../modules/wrc_core/wrc_dpram.vhd \ ../../modules/wrc_core/wrc_dpram.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \ ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../top/spec_ref_design/spec_wr_ref_top.ucf \ ../../top/spec_ref_design/spec_wr_ref_top.ucf \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd \
../../modules/wr_eca/eca_rmw.vhd \
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../modules/wr_dacs/spec_serial_dac.vhd \ ../../modules/wr_dacs/spec_serial_dac.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \ ../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \ ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../modules/fabric/xwb_fabric_source.vhd \ ../../modules/fabric/xwb_fabric_source.vhd \
../../modules/wr_eca/eca_tlu_auto.vhd \ ../../modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \ ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../modules/wr_streamers/gc_escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../modules/wr_streamers/xwr_transmission.vhd \ ../../modules/wr_streamers/xwr_transmission.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \ ../../modules/wr_streamers/dropping_buffer.vhd \
../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd \
../../modules/wr_softpll_ng/spll_wb_slave.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \ ../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \ ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \ ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \ ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \ ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \ ../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \ ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
../../modules/wr_endpoint/ep_autonegotiation.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \ ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../modules/wr_eca/eca.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \ ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \ ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd \
../../modules/wr_endpoint/ep_rx_early_address_match.vhd \ ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/wr_si57x_interface/wr_si57x_interface.vhd \ ../../modules/wr_eca/eca_sdp.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \ ../../modules/wr_eca/eca_data.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../modules/wr_streamers/gc_escape_detector.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../modules/wr_eca/eca_queue_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
../../modules/wr_eca/eca_walker.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
../../modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../modules/wrc_core/wrc_syscon_pkg.vhd \
../../modules/wr_eca/eca_tlu_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../platform/xilinx/chipscope/chipscope_icon.ngc \
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../modules/wr_eca/wr_eca.vhd \
../../modules/wr_eca/eca_offset.vhd \
../../modules/wr_endpoint/ep_crc32_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../board/common/wr_board_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd \
../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../modules/fabric/wr_fabric_pkg.vhd \
../../modules/wr_eca/eca_scan.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \ ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \ ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
spec_wr_ref.xise \ ../../modules/wr_eca/eca_scubus_channel.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \ ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../modules/wr_endpoint/wr_endpoint.vhd \ ../../modules/timing/pulse_stamper.vhd \
../../modules/wr_softpll_ng/spll_period_detect.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../modules/fabric/xwrf_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../modules/wr_eca/eca_rmw.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd \
../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../modules/timing/hpll_period_detect.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \ ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_eca/eca_ac_wbm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../modules/wr_eca/eca_data.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \ ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../modules/wr_eca/eca_queue.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \ ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \ ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../modules/wr_endpoint/ep_rx_buffer.vhd \ ../../modules/wr_endpoint/ep_rx_buffer.vhd \
../../modules/wr_mini_nic/minic_packet_buffer.vhd \ ../../modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../modules/wr_eca/eca_internals_pkg.vhd \ ../../modules/wr_eca/eca_internals_pkg.vhd \
../../modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \ ../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \ ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \ ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \ ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../modules/wr_streamers/gc_escape_detector.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../modules/timing/pulse_gen.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \ ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \ ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../board/spec/wrc_board_spec.vhd \ ../../board/spec/wrc_board_spec.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../modules/wrc_core/wb_reset.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../modules/wr_eca/eca_tdp.vhd \ ../../modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../modules/wr_eca/eca_search.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \ ../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \ ../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
../../modules/wr_eca/eca_queue_auto.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../top/spec_ref_design/spec_wr_ref_top.vhd \
../../modules/wr_eca/eca_wr_time.vhd \ ../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \ ../../modules/wr_streamers/xrx_streamer.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \ ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
../../modules/wr_eca/eca_walker.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
../../modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
#target for running synthesis in the remote location #target for running synthesis in the remote location
remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
......
syn/spec_ref_design/spec_wr_ref.xise
View file @ 20e019e0
...@@ -358,948 +358,1005 @@ ...@@ -358,948 +358,1005 @@
<file xil_pn:name="../../modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file> </file>
<file xil_pn:name="../../modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file> </file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file> </file>
<file xil_pn:name="../../modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file> </file>
<file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file> </file>
<file xil_pn:name="../../modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/> <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file> </file>
<file xil_pn:name="../../board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/> <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file> </file>
<file xil_pn:name="../../modules/wr_eca/eca_msi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file> </file>
<file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/> <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/> <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file> </file>
<file xil_pn:name="../../modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_eca/eca_msi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/> <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="../../modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/> <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file> </file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/> <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/> <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file> </file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="338"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="339"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="340"/>
</file>
</files> </files>
<bindings/> <bindings/>
......
syn/svec_ref_design/Makefile 0 → 100644
View file @ 20e019e0
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := svec_wr_ref.xise
ISE_CRAP := *.b svec_wr_ref_top_summary.html *.tcl svec_wr_ref_top.bld svec_wr_ref_top.cmd_log *.drc svec_wr_ref_top.lso *.ncd svec_wr_ref_top.ngc svec_wr_ref_top.ngd svec_wr_ref_top.ngr svec_wr_ref_top.pad svec_wr_ref_top.par svec_wr_ref_top.pcf svec_wr_ref_top.prj svec_wr_ref_top.ptwx svec_wr_ref_top.stx svec_wr_ref_top.syr svec_wr_ref_top.twr svec_wr_ref_top.twx svec_wr_ref_top.gise $(PROJECT).gise svec_wr_ref_top.bgn svec_wr_ref_top.unroutes svec_wr_ref_top.ut svec_wr_ref_top.xpi svec_wr_ref_top.xst svec_wr_ref_top_bitgen.xwbt svec_wr_ref_top_envsettings.html svec_wr_ref_top_guide.ncd svec_wr_ref_top_map.map svec_wr_ref_top_map.mrp svec_wr_ref_top_map.ncd svec_wr_ref_top_map.ngm svec_wr_ref_top_map.xrpt svec_wr_ref_top_ngdbuild.xrpt svec_wr_ref_top_pad.csv svec_wr_ref_top_pad.txt svec_wr_ref_top_par.xrpt svec_wr_ref_top_summary.xml svec_wr_ref_top_usage.xml svec_wr_ref_top_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Synthesize - XST}" >> run.tcl
echo "process run {Translate}" >> run.tcl
echo "process run {Map}" >> run.tcl
echo "process run {Place & Route}" >> run.tcl
echo "process run {Generate Programming File}" >> run.tcl
synthesis:
/home/greg/opt/Xilinx/14.5/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
syn_post_cmd:
syn_pre_cmd:
#target for cleaning all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
R_NAME:=greg/svec_wr_ref
PORT:=22
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
CWD := $(shell pwd)
FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd \
../../modules/wr_dacs/spec_serial_dac_arb.vhd \
../../modules/wr_endpoint/ep_wishbone_controller.vhd \
../../modules/wr_eca/eca_free.vhd \
../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \
../../modules/wr_eca/eca_msi.vhd \
../../modules/wr_endpoint/wr_endpoint.vhd \
../../modules/wr_tlu/tlu_fsm.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../modules/wr_eca/eca_ac_wbm_auto.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../modules/wr_endpoint/endpoint_pkg.vhd \
../../modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd \
../../modules/wr_eca/eca_wb_event.vhd \
../../modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../modules/wr_tlu/tlu.vhd \
../../top/svec_ref_design/svec_wr_ref_top.ucf \
../../modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../modules/wr_streamers/rx_streamer.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
../../modules/wr_endpoint/ep_autonegotiation.vhd \
../../board/common/xwrc_board_common.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../modules/wr_eca/eca_queue.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/wr_streamers/gc_escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../modules/wrc_core/wb_reset.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd \
../../board/svec/wr_svec_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../modules/wr_endpoint/ep_leds_controller.vhd \
../../modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
../../modules/wr_tbi_phy/dec_8b10b.vhd \
../../modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../modules/wr_endpoint/ep_tx_path.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../modules/wrc_core/wrc_periph.vhd \
../../modules/wr_eca/eca_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../modules/wrc_core/wr_core.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../modules/wr_streamers/wr_transmission_wb.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \
../../platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd \
../../modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd \
../../modules/fabric/xwb_fabric_sink.vhd \
../../modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../modules/wrc_core/wrc_syscon_wb.vhd \
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../board/svec/xwrc_board_svec.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../modules/wr_eca/eca.vhd \
../../modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../modules/wr_softpll_ng/spll_period_detect.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../modules/wr_eca/eca_ac_wbm.vhd \
svec_wr_ref.xise \
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../modules/timing/pulse_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
../../modules/wr_eca/eca_search.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
../../top/svec_ref_design/svec_wr_ref_top.vhd \
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../modules/wr_tlu/tlu_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../modules/timing/multi_dmtd_with_deglitcher.vhd \
../../modules/wr_endpoint/ep_tx_header_processor.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../modules/wr_eca/eca_channel.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../modules/wr_eca/eca_auto.vhd \
../../modules/wr_eca/eca_tlu.vhd \
../../modules/wrc_core/xwr_syscon_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../modules/wr_streamers/xrtx_streamers_stats.vhd \
../../modules/fabric/xwrf_reg.vhd \
../../modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../platform/xilinx/xwrc_platform_xilinx.vhd \
../../modules/wr_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../modules/wr_eca/eca_adder.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \
../../modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../modules/wr_dacs/spec_serial_dac.vhd \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../modules/fabric/xwb_fabric_source.vhd \
../../modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../modules/wr_streamers/xwr_transmission.vhd \
../../modules/wr_streamers/dropping_buffer.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../board/svec/wrc_board_svec.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/wr_eca/eca_sdp.vhd \
../../modules/wr_eca/eca_data.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../modules/wr_streamers/gc_escape_detector.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../modules/wr_eca/eca_queue_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
../../modules/wr_eca/eca_walker.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
../../modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../modules/wrc_core/wrc_syscon_pkg.vhd \
../../modules/wr_eca/eca_tlu_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../platform/xilinx/chipscope/chipscope_icon.ngc \
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../modules/wr_eca/wr_eca.vhd \
../../modules/wr_eca/eca_offset.vhd \
../../modules/wr_endpoint/ep_crc32_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../board/common/wr_board_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd \
../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../modules/fabric/wr_fabric_pkg.vhd \
../../modules/wr_eca/eca_scan.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../modules/wr_eca/eca_scubus_channel.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../modules/timing/pulse_stamper.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../modules/fabric/xwrf_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../modules/wr_eca/eca_rmw.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd \
../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../modules/timing/hpll_period_detect.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
run.tcl \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../modules/wr_endpoint/ep_rx_buffer.vhd \
../../modules/wr_mini_nic/minic_packet_buffer.vhd \
../../modules/wr_eca/eca_internals_pkg.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
#target for running synthesis in the remote location
remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
else
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
endif
sync:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/svec_ref_design/svec_wr_ref.xise 0 → 100644
View file @ 20e019e0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_wr_ref_top" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="340"/>
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</files>
<bindings/>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
</project>
syn/vfchd_ref_design/Makefile 0 → 100644
View file @ 20e019e0
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := vfchd_wr_ref
QUARTUS_CRAP := $(PROJECT).asm.rpt $(PROJECT).done $(PROJECT).fit.rpt $(PROJECT).fit.smsg $(PROJECT).fit.summary $(PROJECT).flow.rpt $(PROJECT).jdi $(PROJECT).map.rpt $(PROJECT).map.summary $(PROJECT).pin $(PROJECT).qws $(PROJECT).sta.rpt $(PROJECT).sta.summary run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
echo "load_package flow" > run.tcl
echo "project_open $(PROJECT)" >> run.tcl
echo "execute_flow -compile" >> run.tcl
/opt/altera/16.0/quartus/bin/quartus_sh -t run.tcl
check_tool:
syn_post_cmd:
syn_pre_cmd:
#target for cleaing all intermediate stuff
clean:
rm -f $(QUARTUS_CRAP)
rm -rf db incremental_db
#target for cleaning final files
mrproper:
rm -f *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
syn/vfchd_ref_design/vfchd_wr_ref.qpf 0 → 100644
View file @ 20e019e0
PROJECT_REVISION = "vfchd_wr_ref"
syn/vfchd_ref_design/vfchd_wr_ref.qsf 0 → 100644
View file @ 20e019e0
set_global_assignment -name FAMILY "Arria V"
set_global_assignment -name DEVICE 5AGXMB1G4F40C4
set_global_assignment -name TOP_LEVEL_ENTITY vfchd_wr_ref_top
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
set_location_assignment PIN_AW25 -to areset_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to areset_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to areset_n_i
set_location_assignment PIN_AF8 -to clk_board_125m_i
set_instance_assignment -name IO_STANDARD LVDS -to clk_board_125m_i
set_location_assignment PIN_AD20 -to clk_board_20m_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_board_20m_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to clk_board_20m_i
set_location_assignment PIN_AF25 -to dac_dmtd_sync_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_dmtd_sync_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dac_dmtd_sync_n_o
set_instance_assignment -name SLEW_RATE 1 -to dac_dmtd_sync_n_o
set_location_assignment PIN_AC24 -to dac_ref_sync_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_ref_sync_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dac_ref_sync_n_o
set_instance_assignment -name SLEW_RATE 1 -to dac_ref_sync_n_o
set_location_assignment PIN_AH26 -to dac_sclk_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_sclk_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dac_sclk_o
set_instance_assignment -name SLEW_RATE 1 -to dac_sclk_o
set_location_assignment PIN_AG26 -to dac_din_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_din_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dac_din_o
set_instance_assignment -name SLEW_RATE 1 -to dac_din_o
set_location_assignment PIN_AE1 -to sfp_rx_i
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to sfp_rx_i
set_location_assignment PIN_AD3 -to sfp_tx_o
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to sfp_tx_o
set_location_assignment PIN_AN25 -to i2c_mux_sda_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to i2c_mux_sda_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to i2c_mux_sda_b
set_instance_assignment -name SLEW_RATE 1 -to i2c_mux_sda_b
set_location_assignment PIN_AM25 -to i2c_mux_scl_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to i2c_mux_scl_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to i2c_mux_scl_b
set_instance_assignment -name SLEW_RATE 1 -to i2c_mux_scl_b
set_location_assignment PIN_AT26 -to io_exp_irq_bsteth_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to io_exp_irq_bsteth_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to io_exp_irq_bsteth_n_i
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_exp_irq_bsteth_n_i
set_location_assignment PIN_AK25 -to io_exp_irq_los_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to io_exp_irq_los_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to io_exp_irq_los_n_i
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_exp_irq_los_n_i
set_location_assignment PIN_AD26 -to eeprom_sda_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to eeprom_sda_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to eeprom_sda_b
set_instance_assignment -name SLEW_RATE 1 -to eeprom_sda_b
set_location_assignment PIN_AH25 -to eeprom_scl_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to eeprom_scl_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to eeprom_scl_b
set_instance_assignment -name SLEW_RATE 1 -to eeprom_scl_b
set_location_assignment PIN_AV27 -to onewire_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to onewire_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to onewire_b
set_instance_assignment -name SLEW_RATE 1 -to onewire_b
set_location_assignment PIN_AW28 -to vme_write_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_write_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_write_n_i
set_location_assignment PIN_AW30 -to vme_lword_n_b
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_lword_n_b
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_lword_n_b
set_instance_assignment -name SLEW_RATE 1 -to vme_lword_n_b
set_location_assignment PIN_AK21 -to vme_iackout_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_iackout_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_iackout_n_o
set_instance_assignment -name SLEW_RATE 1 -to vme_iackout_n_o
set_location_assignment PIN_AM21 -to vme_iackin_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_iackin_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_iackin_n_i
set_location_assignment PIN_AN21 -to vme_iack_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_iack_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_iack_n_i
set_location_assignment PIN_AL22 -to vme_dtack_oe_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_dtack_oe_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_dtack_oe_o
set_instance_assignment -name SLEW_RATE 1 -to vme_dtack_oe_o
set_location_assignment PIN_AP22 -to vme_ds_n_i[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_ds_n_i[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_ds_n_i[0]
set_location_assignment PIN_AN22 -to vme_ds_n_i[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_ds_n_i[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_ds_n_i[1]
set_location_assignment PIN_AW20 -to vme_data_oe_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_oe_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_oe_n_o
set_instance_assignment -name SLEW_RATE 1 -to vme_data_oe_n_o
set_location_assignment PIN_AW19 -to vme_data_dir_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_dir_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_dir_o
set_instance_assignment -name SLEW_RATE 1 -to vme_data_dir_o
set_location_assignment PIN_AE29 -to vme_as_n_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_as_n_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_as_n_i
set_location_assignment PIN_AK27 -to vme_addr_oe_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_oe_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_oe_n_o
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_oe_n_o
set_location_assignment PIN_AJ27 -to vme_addr_dir_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_dir_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_dir_o
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_dir_o
set_location_assignment PIN_AK22 -to vme_irq_n_o[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[1]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[1]
set_location_assignment PIN_AT21 -to vme_irq_n_o[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[2]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[2]
set_location_assignment PIN_AR21 -to vme_irq_n_o[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[3]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[3]
set_location_assignment PIN_AH22 -to vme_irq_n_o[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[4]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[4]
set_location_assignment PIN_AG22 -to vme_irq_n_o[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[5]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[5]
set_location_assignment PIN_AU20 -to vme_irq_n_o[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[6]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[6]
set_location_assignment PIN_AT20 -to vme_irq_n_o[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_n_o[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_n_o[7]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_n_o[7]
set_location_assignment PIN_AD24 -to vme_data_b[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[0]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[0]
set_location_assignment PIN_AD23 -to vme_data_b[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[1]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[1]
set_location_assignment PIN_AU24 -to vme_data_b[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[2]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[2]
set_location_assignment PIN_AT24 -to vme_data_b[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[3]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[3]
set_location_assignment PIN_AL24 -to vme_data_b[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[4]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[4]
set_location_assignment PIN_AK24 -to vme_data_b[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[5]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[5]
set_location_assignment PIN_AF24 -to vme_data_b[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[6]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[6]
set_location_assignment PIN_AE24 -to vme_data_b[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[7]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[7]
set_location_assignment PIN_AH24 -to vme_data_b[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[8]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[8]
set_location_assignment PIN_AG24 -to vme_data_b[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[9]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[9]
set_location_assignment PIN_AW24 -to vme_data_b[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[10]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[10]
set_location_assignment PIN_AW23 -to vme_data_b[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[11]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[11]
set_location_assignment PIN_AP24 -to vme_data_b[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[12]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[12]
set_location_assignment PIN_AN24 -to vme_data_b[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[13]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[13]
set_location_assignment PIN_AU23 -to vme_data_b[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[14]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[14]
set_location_assignment PIN_AT23 -to vme_data_b[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[15]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[15]
set_location_assignment PIN_AP23 -to vme_data_b[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[16]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[16]
set_location_assignment PIN_AN23 -to vme_data_b[17]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[17]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[17]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[17]
set_location_assignment PIN_AE23 -to vme_data_b[18]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[18]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[18]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[18]
set_location_assignment PIN_AD22 -to vme_data_b[19]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[19]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[19]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[19]
set_location_assignment PIN_AL23 -to vme_data_b[20]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[20]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[20]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[20]
set_location_assignment PIN_AK23 -to vme_data_b[21]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[21]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[21]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[21]
set_location_assignment PIN_AU22 -to vme_data_b[22]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[22]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[22]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[22]
set_location_assignment PIN_AT22 -to vme_data_b[23]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[23]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[23]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[23]
set_location_assignment PIN_AW22 -to vme_data_b[24]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[24]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[24]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[24]
set_location_assignment PIN_AV22 -to vme_data_b[25]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[25]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[25]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[25]
set_location_assignment PIN_AW21 -to vme_data_b[26]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[26]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[26]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[26]
set_location_assignment PIN_AV21 -to vme_data_b[27]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[27]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[27]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[27]
set_location_assignment PIN_AH23 -to vme_data_b[28]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[28]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[28]
set_location_assignment PIN_AG23 -to vme_data_b[29]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[29]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[29]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[29]
set_location_assignment PIN_AF22 -to vme_data_b[30]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[30]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[30]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[30]
set_location_assignment PIN_AE22 -to vme_data_b[31]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_data_b[31]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_data_b[31]
set_instance_assignment -name SLEW_RATE 1 -to vme_data_b[31]
set_location_assignment PIN_AD29 -to vme_am_i[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[0]
set_location_assignment PIN_AH30 -to vme_am_i[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[1]
set_location_assignment PIN_AG30 -to vme_am_i[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[2]
set_location_assignment PIN_AV31 -to vme_am_i[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[3]
set_location_assignment PIN_AU31 -to vme_am_i[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[4]
set_location_assignment PIN_AW31 -to vme_am_i[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_am_i[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_am_i[5]
set_location_assignment PIN_AL30 -to vme_addr_b[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[1]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[1]
set_location_assignment PIN_AK30 -to vme_addr_b[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[2]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[2]
set_location_assignment PIN_AT30 -to vme_addr_b[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[3]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[3]
set_location_assignment PIN_AR30 -to vme_addr_b[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[4]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[4]
set_location_assignment PIN_AV30 -to vme_addr_b[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[5]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[5]
set_location_assignment PIN_AU30 -to vme_addr_b[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[6]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[6]
set_location_assignment PIN_AU29 -to vme_addr_b[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[7]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[7]
set_location_assignment PIN_AT29 -to vme_addr_b[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[8]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[8]
set_location_assignment PIN_AP30 -to vme_addr_b[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[9]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[9]
set_location_assignment PIN_AN30 -to vme_addr_b[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[10]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[10]
set_location_assignment PIN_AP29 -to vme_addr_b[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[11]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[11]
set_location_assignment PIN_AN29 -to vme_addr_b[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[12]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[12]
set_location_assignment PIN_AC29 -to vme_addr_b[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[13]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[13]
set_location_assignment PIN_AB29 -to vme_addr_b[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[14]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[14]
set_location_assignment PIN_AG28 -to vme_addr_b[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[15]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[15]
set_location_assignment PIN_AF28 -to vme_addr_b[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[16]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[16]
set_location_assignment PIN_AL29 -to vme_addr_b[17]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[17]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[17]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[17]
set_location_assignment PIN_AK29 -to vme_addr_b[18]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[18]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[18]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[18]
set_location_assignment PIN_AJ28 -to vme_addr_b[19]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[19]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[19]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[19]
set_location_assignment PIN_AH28 -to vme_addr_b[20]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[20]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[20]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[20]
set_location_assignment PIN_AE28 -to vme_addr_b[21]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[21]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[21]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[21]
set_location_assignment PIN_AD28 -to vme_addr_b[22]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[22]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[22]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[22]
set_location_assignment PIN_AB28 -to vme_addr_b[23]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[23]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[23]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[23]
set_location_assignment PIN_AB27 -to vme_addr_b[24]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[24]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[24]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[24]
set_location_assignment PIN_AM28 -to vme_addr_b[25]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[25]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[25]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[25]
set_location_assignment PIN_AD27 -to vme_addr_b[26]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[26]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[26]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[26]
set_location_assignment PIN_AC27 -to vme_addr_b[27]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[27]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[27]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[27]
set_location_assignment PIN_AR28 -to vme_addr_b[28]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[28]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[28]
set_location_assignment PIN_AP28 -to vme_addr_b[29]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[29]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[29]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[29]
set_location_assignment PIN_AV28 -to vme_addr_b[30]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[30]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[30]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[30]
set_location_assignment PIN_AU28 -to vme_addr_b[31]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_addr_b[31]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_addr_b[31]
set_instance_assignment -name SLEW_RATE 1 -to vme_addr_b[31]
set_location_assignment PIN_AM27 -to fmc_enable_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to fmc_enable_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to fmc_enable_n_o
set_instance_assignment -name SLEW_RATE 1 -to fmc_enable_n_o
set_location_assignment PIN_C20 -to dio_led_term_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio_led_term_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio_led_term_o
set_instance_assignment -name SLEW_RATE 1 -to dio_led_term_o
set_location_assignment PIN_D20 -to dio_led_out_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio_led_out_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio_led_out_o
set_instance_assignment -name SLEW_RATE 1 -to dio_led_out_o
set_location_assignment PIN_M27 -to dio1_i
set_instance_assignment -name IO_STANDARD LVDS -to dio1_i
set_location_assignment PIN_AK34 -to dio5_clk_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio5_clk_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio5_clk_i
set_location_assignment PIN_R26 -to dio1_oe_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio1_oe_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio1_oe_n_o
set_instance_assignment -name SLEW_RATE 1 -to dio1_oe_n_o
set_location_assignment PIN_C28 -to dio5_oe_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio5_oe_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio5_oe_n_o
set_instance_assignment -name SLEW_RATE 1 -to dio5_oe_n_o
set_location_assignment PIN_T27 -to dio1_term_en_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio1_term_en_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio1_term_en_o
set_instance_assignment -name SLEW_RATE 1 -to dio1_term_en_o
set_location_assignment PIN_C27 -to dio5_term_en_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio5_term_en_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio5_term_en_o
set_instance_assignment -name SLEW_RATE 1 -to dio5_term_en_o
set_location_assignment PIN_AL26 -to vfchd_gpio3_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vfchd_gpio3_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vfchd_gpio3_o
set_instance_assignment -name SLEW_RATE 1 -to vfchd_gpio3_o
set_location_assignment PIN_AV24 -to vfchd_gpio4_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vfchd_gpio4_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vfchd_gpio4_o
set_instance_assignment -name SLEW_RATE 1 -to vfchd_gpio4_o
set_location_assignment PIN_D25 -to dio4_i
set_instance_assignment -name IO_STANDARD LVDS -to dio4_i
set_location_assignment PIN_M29 -to dio4_oe_n_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio4_oe_n_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio4_oe_n_o
set_instance_assignment -name SLEW_RATE 1 -to dio4_oe_n_o
set_location_assignment PIN_B27 -to dio4_term_en_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to dio4_term_en_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to dio4_term_en_o
set_instance_assignment -name SLEW_RATE 1 -to dio4_term_en_o
set_location_assignment PIN_AH21 -to vfchd_gpio1_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vfchd_gpio1_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vfchd_gpio1_o
set_instance_assignment -name SLEW_RATE 1 -to vfchd_gpio1_o
set_location_assignment PIN_AG21 -to vfchd_gpio2_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vfchd_gpio2_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vfchd_gpio2_o
set_instance_assignment -name SLEW_RATE 1 -to vfchd_gpio2_o
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/wr_pps_gen.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/dec_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_sync_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_wishbone_controller.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/enc_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_fsm.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_free.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rtu_header_extract.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_periph.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_wr_ref_top.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_oob_insert.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_msi.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wr_core.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/multi_dmtd_with_deglitcher.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/xwr_mini_nic.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_header_processor.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_channel.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/wr_eca.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_offset.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_crc32_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wb_event.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_fsm.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_transmission_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wb_slave.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_sdp.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scan.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrtx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/dropping_buffer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_reg.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_phase_meas.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/xwrc_platform_altera.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scubus_channel.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_stamper.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/streamers_pkg.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/endpoint_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/rx_streamer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_with_deglitcher.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_timestamping_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_sink.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/si570_if_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_wb_master.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrcore_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_adder.vhd
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
set_global_assignment -name SDC_FILE vfchd_wr_ref.sdc
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_mux.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_piso_fifo.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_dpram.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwr_core.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_rmw.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/xwr_pps_gen.vhd
set_global_assignment -name VHDL_FILE ../../board/common/xwrc_board_common.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_source.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/wr_tbi_phy.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/gc_escape_inserter.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xwr_transmission.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wb_slave.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/hpll_period_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/pps_gen_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/sfp_i2c_adapter.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/xwr_endpoint.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_autonegotiation.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_packet_injection.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/endpoint_private_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
set_global_assignment -name VHDL_FILE ../../board/common/wr_board_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_early_address_match.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/wr_si57x_interface.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_aligner.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/wr_endpoint.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wr_vfchd_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_period_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wr_time.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_ts_counter.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_data.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
set_global_assignment -name VHDL_FILE ../../board/vfchd/xwrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_buffer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_packet_buffer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xtx_streamer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/wr_mini_nic.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/matrix_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/gc_escape_detector.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/wr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_1000basex_pcs.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wb_reset.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tag_channel.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tdp.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_search.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/tx_streamer.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrx_streamer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_leds_controller.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_walker.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/softpll_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_packet_filter.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:quartus_preflow.tcl"
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_phy/arria5_phy8.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_phy/arria5_phy16.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_phy/arria5_phy_reconf.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_dmtd_pll_default.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_ext_ref_pll_default.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.qip
\ No newline at end of file
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