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Commit 1272b672 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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platform/xilinx: remove unnecesary files for Ultrascale family

parent 0fbb5a20
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        platform/xilinx/wr_gtp_phy/Manifest.py
        View file @ 1272b672
        ......@@ -62,15 +62,11 @@ elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
        ......@@ -80,7 +76,6 @@ elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
        "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v",
        "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2.v",
        "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_top.v",
        "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
        ......
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/Manifest.py
        View file @ 1272b672
        ......@@ -2,15 +2,11 @@ files = ["common/gtwizard_ultrascale_v1_7_bit_sync.v",
        "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
        "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
        "common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
        "common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v",
        "common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
        "common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
        "common/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
        "common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v",
        "common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
        "common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
        "common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
        ......@@ -20,7 +16,6 @@ files = ["common/gtwizard_ultrascale_v1_7_bit_sync.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
        "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
        "common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
        "common/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v",
        "synth/gtwizard_ultrascale_2.v",
        "synth/gtwizard_ultrascale_2_gtwizard_top.v",
        "synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
        ......
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v deleted 100755 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        // ***************************
        // * DO NOT MODIFY THIS FILE *
        // ***************************
        `timescale 1ps/1ps
        module gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_freq_counter # (
        parameter REVISION = 1
        )(
        output reg [17:0] freq_cnt_o = 18'd0,
        output reg done_o,
        input wire rst_i,
        input wire [15:0] test_term_cnt_i,
        input wire ref_clk_i,
        input wire test_clk_i
        );
        //****************************************************************************
        // Local Parameters
        //****************************************************************************
        localparam RESET_STATE = 0;
        localparam MEASURE_STATE = 1;
        localparam HOLD_STATE = 2;
        localparam UPDATE_STATE = 3;
        localparam DONE_STATE = 4;
        //****************************************************************************
        // Local Signals
        //****************************************************************************
        reg [17:0] testclk_cnt = 18'h00000;
        reg [15:0] refclk_cnt = 16'h0000;
        reg [3:0] testclk_div4 = 4'h1;
        wire testclk_rst;
        wire testclk_en;
        reg [5:0] hold_clk = 6'd0;
        reg [4:0] state = 5'd1;
        (* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
        (* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
        //
        // need to get testclk_rst into TESTCLK_I domain
        //
        always @(posedge test_clk_i)
        begin
        tstclk_rst_dly1 <= testclk_rst;
        tstclk_rst_dly2 <= tstclk_rst_dly1;
        end
        //
        // need to get testclk_en into TESTCLK_I domain
        //
        always @(posedge test_clk_i)
        begin
        testclk_en_dly1 <= testclk_en;
        testclk_en_dly2 <= testclk_en_dly1;
        end
        always @(posedge test_clk_i)
        begin
        if (tstclk_rst_dly2 == 1'b1)
        begin
        testclk_div4 <= 4'h1;
        end
        else
        begin
        testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
        end
        end
        wire testclk_rst_sync;
        gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_testclk_rst_inst (
        .clk_in (test_clk_i),
        .rst_in (testclk_rst),
        .rst_out (testclk_rst_sync)
        );
        always @(posedge test_clk_i or posedge testclk_rst_sync)
        begin
        if (testclk_rst_sync == 1'b1)
        begin
        testclk_cnt <= 0;
        end
        else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
        begin
        testclk_cnt <= testclk_cnt + 1;
        end
        end
        /* always @(posedge test_clk_i or posedge testclk_rst)
        begin
        if (testclk_rst == 1'b1)
        begin
        testclk_cnt <= 0;
        end
        else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
        begin
        testclk_cnt <= testclk_cnt + 1;
        end
        end */
        always @(posedge ref_clk_i or posedge rst_i)
        begin
        if (rst_i)
        done_o <= 1'b0;
        else
        done_o <= state[DONE_STATE];
        end
        always @(posedge ref_clk_i or posedge rst_i)
        begin
        if (rst_i) begin
        state <= 0;
        state[RESET_STATE] <= 1'b1;
        end
        else begin
        state <= 0;
        case (1'b1) // synthesis parallel_case full_case
        state[RESET_STATE]:
        begin
        if (hold_clk == 6'h3F)
        state[MEASURE_STATE] <= 1'b1;
        else
        state[RESET_STATE] <= 1'b1;
        end
        state[MEASURE_STATE]:
        begin
        if (refclk_cnt == test_term_cnt_i)
        state[HOLD_STATE] <= 1'b1;
        else
        state[MEASURE_STATE] <= 1'b1;
        end
        state[HOLD_STATE]:
        begin
        if (hold_clk == 6'hF)
        state[UPDATE_STATE] <= 1'b1;
        else
        state[HOLD_STATE] <= 1'b1;
        end
        state[UPDATE_STATE]:
        begin
        freq_cnt_o <= testclk_cnt;
        state[DONE_STATE] <= 1'b1;
        end
        state[DONE_STATE]:
        begin
        state[DONE_STATE] <= 1'b1;
        end
        endcase
        end
        end
        assign testclk_rst = state[RESET_STATE];
        assign testclk_en = state[MEASURE_STATE];
        always @(posedge ref_clk_i)
        begin
        if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
        hold_clk <= hold_clk + 1;
        else
        hold_clk <= 0;
        end
        always @(posedge ref_clk_i)
        begin
        if (state[MEASURE_STATE] == 1'b1)
        refclk_cnt <= refclk_cnt + 1;
        else
        refclk_cnt <= 0;
        end
        endmodule
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v deleted 100755 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        // ***************************
        // * DO NOT MODIFY THIS FILE *
        // ***************************
        `timescale 1ps/1ps
        module gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal # (
        parameter integer C_RX_PLL_TYPE = 0,
        parameter integer C_TX_PLL_TYPE = 0,
        parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
        parameter SIM_RESET_SPEEDUP = "TRUE",
        parameter C_FREERUN_FREQUENCY = 100,
        parameter REVISION = 2,
        parameter C_PCIE_ENABLE = "FALSE",
        parameter C_PCIE_CORECLK_FREQ = 250
        )(
        // control signals
        input wire [17:0] TXOUTCLK_PERIOD_IN,
        input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
        input wire [17:0] CNT_TOL_IN,
        input wire [15:0] FREQ_COUNT_WINDOW_IN,
        // User Interface
        input wire RESET_IN,
        input wire CLK_IN,
        input wire DRPRST_IN,
        input wire [1:0] USER_TXPLLCLKSEL,
        input wire [1:0] USER_RXPLLCLKSEL,
        input wire USER_RXPROGDIVRESET_IN,
        output wire USER_RXPRGDIVRESETDONE_OUT,
        output wire USER_RXPMARESETDONE_OUT,
        input wire [2:0] USER_RXOUTCLKSEL_IN,
        input wire USER_RXOUTCLK_BUFG_CE_IN,
        input wire USER_RXOUTCLK_BUFG_CLR_IN,
        input wire USER_GTRXRESET_IN,
        input wire USER_RXCDRHOLD_IN,
        input wire USER_RXPMARESET_IN,
        input wire USER_TXPROGDIVRESET_IN,
        output wire USER_TXPRGDIVRESETDONE_OUT,
        input wire [2:0] USER_TXOUTCLKSEL_IN,
        input wire USER_TXOUTCLK_BUFG_CE_IN,
        input wire USER_TXOUTCLK_BUFG_CLR_IN,
        output wire USER_CPLLLOCK_OUT,
        input wire [9:0] USER_CHANNEL_DRPADDR_IN,
        input wire [15:0] USER_CHANNEL_DRPDI_IN,
        input wire USER_CHANNEL_DRPEN_IN,
        input wire USER_CHANNEL_DRPWE_IN,
        output wire USER_CHANNEL_DRPRDY_OUT,
        output wire [15:0] USER_CHANNEL_DRPDO_OUT,
        // Debug Interface
        output wire CPLL_CAL_FAIL,
        output wire CPLL_CAL_DONE,
        output wire [15:0] DEBUG_OUT,
        output wire [17:0] CAL_FREQ_CNT,
        input [3:0] REPEAT_RESET_LIMIT,
        // GT Interface
        input wire GTYE4_TXOUTCLK_IN,
        input wire GTYE4_RXOUTCLK_IN,
        input wire GTYE4_CPLLLOCK_IN,
        output wire GTYE4_CPLLRESET_OUT,
        output wire GTYE4_RXCDRHOLD_OUT,
        output wire GTYE4_GTRXRESET_OUT,
        output wire GTYE4_RXPMARESET_OUT,
        output wire GTYE4_RXPROGDIVRESET_OUT,
        output wire [2:0] GTYE4_RXOUTCLKSEL_OUT,
        input wire GTYE4_RXPRGDIVRESETDONE_IN,
        input wire GTYE4_RXPMARESETDONE_IN,
        output wire GTYE4_CPLLPD_OUT,
        output wire GTYE4_TXPROGDIVRESET_OUT,
        output wire [2:0] GTYE4_TXOUTCLKSEL_OUT,
        input wire GTYE4_TXPRGDIVRESETDONE_IN,
        output wire [9:0] GTYE4_CHANNEL_DRPADDR_OUT,
        output wire [15:0] GTYE4_CHANNEL_DRPDI_OUT,
        output wire GTYE4_CHANNEL_DRPEN_OUT,
        output wire GTYE4_CHANNEL_DRPWE_OUT,
        input wire GTYE4_CHANNEL_DRPRDY_IN,
        input wire [15:0] GTYE4_CHANNEL_DRPDO_IN
        );
        wire rx_done;
        wire tx_done;
        wire cal_on_rx_cal_fail;
        wire cal_on_rx_cal_done;
        wire [15:0] cal_on_rx_debug_out;
        wire [17:0] cal_on_rx_cal_freq_cnt;
        wire cal_on_rx_cpllreset_out;
        wire cal_on_rx_cpllpd_out;
        wire cal_on_rx_cplllock_out;
        wire cal_on_rx_drpen_out;
        wire cal_on_rx_drpwe_out;
        wire [9:0] cal_on_rx_drpaddr_out;
        wire [15:0] cal_on_rx_drpdi_out;
        wire [15:0] cal_on_rx_dout;
        wire cal_on_rx_drdy;
        wire cal_on_tx_cal_fail;
        wire cal_on_tx_cal_done;
        wire [15:0] cal_on_tx_debug_out;
        wire [17:0] cal_on_tx_cal_freq_cnt;
        wire cal_on_tx_cpllreset_out;
        wire cal_on_tx_cpllpd_out;
        wire cal_on_tx_cplllock_out;
        wire cal_on_tx_drpen_out;
        wire cal_on_tx_drpwe_out;
        wire [9:0] cal_on_tx_drpaddr_out;
        wire [15:0] cal_on_tx_drpdi_out;
        wire [15:0] cal_on_tx_dout;
        wire cal_on_tx_drdy;
        localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
        localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h057; // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
        localparam [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6;
        localparam [9:0] ADDR_X0E1 = 10'h0E1;
        localparam [9:0] ADDR_X079 = 10'h079;
        localparam [9:0] ADDR_X114 = 10'h114;
        localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block
        wire cpll_cal_on_tx_or_rx; //1: RX cal block, 0: TX cal block;
        assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0);
        // TX reset version
        wire cal_on_tx_reset_in;
        assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
        wire cal_on_tx_reset_in_sync;
        gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_resetin_tx_inst (
        .clk_in (CLK_IN),
        .rst_in (cal_on_tx_reset_in),
        .rst_out (cal_on_tx_reset_in_sync)
        );
        // RX reset version
        wire cal_on_rx_reset_in;
        assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;
        wire cal_on_rx_reset_in_sync;
        gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_resetin_rx_inst (
        .clk_in (CLK_IN),
        .rst_in (cal_on_rx_reset_in),
        .rst_out (cal_on_rx_reset_in_sync)
        );
        wire drprst_in_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_drprst_inst (
        .clk_in (CLK_IN),
        .i_in (DRPRST_IN),
        .o_out (drprst_in_sync)
        );
        gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx #
        (
        .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
        .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
        .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
        .C_PCIE_ENABLE(C_PCIE_ENABLE),
        .C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
        ) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i
        (
        // control signals
        .TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
        .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN),
        .CNT_TOL_IN(CNT_TOL_IN),
        .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
        // User Interface
        .RESET_IN(cal_on_tx_reset_in_sync),
        .CLK_IN(CLK_IN),
        .USER_TXPLLCLKSEL(USER_TXPLLCLKSEL),
        .USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN),
        .USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT),
        .USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN),
        .USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN),
        .USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN),
        .USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out),
        // Debug Interface
        .CPLL_CAL_FAIL(cal_on_tx_cal_fail),
        .CPLL_CAL_DONE(cal_on_tx_cal_done),
        .DEBUG_OUT(cal_on_tx_debug_out),
        .CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt),
        .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
        // GT Interface
        .GTYE4_TXOUTCLK_IN(GTYE4_TXOUTCLK_IN),
        .GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
        .GTYE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out),
        .GTYE4_CPLLPD_OUT(cal_on_tx_cpllpd_out),
        .GTYE4_TXPROGDIVRESET_OUT(GTYE4_TXPROGDIVRESET_OUT),
        .GTYE4_TXOUTCLKSEL_OUT(GTYE4_TXOUTCLKSEL_OUT),
        .GTYE4_TXPRGDIVRESETDONE_IN(GTYE4_TXPRGDIVRESETDONE_IN),
        .GTYE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out),
        .GTYE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out),
        .GTYE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out),
        .GTYE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out),
        .GTYE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy),
        .GTYE4_CHANNEL_DRPDO_IN(cal_on_tx_dout),
        .DONE(tx_done)
        );
        gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_rx #
        (
        .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
        .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
        .CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
        .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
        ) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_rx_i
        (
        // control signals
        .RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
        .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN),
        .CNT_TOL_IN(CNT_TOL_IN),
        .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
        // User Interface
        .RESET_IN(cal_on_rx_reset_in_sync),
        .CLK_IN(CLK_IN),
        .USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN),
        .USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT),
        .USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT),
        .USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN),
        .USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN),
        .USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN),
        .USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out),
        .USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN),
        .USER_GTRXRESET_IN(USER_GTRXRESET_IN),
        .USER_RXPMARESET_IN(USER_RXPMARESET_IN),
        // Debug Interface
        .CPLL_CAL_FAIL(cal_on_rx_cal_fail),
        .CPLL_CAL_DONE(cal_on_rx_cal_done),
        .DEBUG_OUT(cal_on_rx_debug_out),
        .CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt),
        .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
        // GT Interface
        .GTYE4_RXOUTCLK_IN(GTYE4_RXOUTCLK_IN),
        .GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
        .GTYE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out),
        .GTYE4_CPLLPD_OUT(cal_on_rx_cpllpd_out),
        .GTYE4_RXPROGDIVRESET_OUT(GTYE4_RXPROGDIVRESET_OUT),
        .GTYE4_RXOUTCLKSEL_OUT(GTYE4_RXOUTCLKSEL_OUT),
        .GTYE4_RXPRGDIVRESETDONE_IN(GTYE4_RXPRGDIVRESETDONE_IN),
        .GTYE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out),
        .GTYE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out),
        .GTYE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out),
        .GTYE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out),
        .GTYE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy),
        .GTYE4_CHANNEL_DRPDO_IN(cal_on_rx_dout),
        .GTYE4_GTRXRESET_OUT(GTYE4_GTRXRESET_OUT),
        .GTYE4_RXPMARESET_OUT(GTYE4_RXPMARESET_OUT),
        .GTYE4_RXCDRHOLD_OUT(GTYE4_RXCDRHOLD_OUT),
        .GTYE4_RXPMARESETDONE_IN(GTYE4_RXPMARESETDONE_IN),
        .DONE(rx_done)
        );
        //OR with TX versions
        assign GTYE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out;
        assign GTYE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out;
        assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out;
        //Mux the debug signals out
        assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done;
        assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail;
        assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out;
        assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt;
        //----------------------------------------------------------------------------------------------
        // DRP ARBITER
        //----------------------------------------------------------------------------------------------
        gtwizard_ultrascale_v1_7_7_gte4_drp_arb #
        (
        .ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
        .ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
        .ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG),
        .ADDR_X0E1(ADDR_X0E1),
        .ADDR_X079(ADDR_X079),
        .ADDR_X114(ADDR_X114),
        .C_NUM_CLIENTS(3),
        .C_ADDR_WIDTH(10),
        .C_DATA_WIDTH(16)
        ) gtwizard_ultrascale_v1_7_7_gte4_drp_arb_i
        (
        .DCLK_I (CLK_IN),
        .RESET_I (drprst_in_sync),
        .DEN_USR_I ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}),
        .DWE_USR_I ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}),
        .DADDR_USR_I ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}),
        .DI_USR_I ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}),
        .DO_USR_O ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}),
        .DRDY_USR_O ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}),
        // arbitrated port
        .DEN_O (GTYE4_CHANNEL_DRPEN_OUT),
        .DWE_O (GTYE4_CHANNEL_DRPWE_OUT),
        .DADDR_O (GTYE4_CHANNEL_DRPADDR_OUT),
        .DI_O (GTYE4_CHANNEL_DRPDI_OUT),
        .DO_I (GTYE4_CHANNEL_DRPDO_IN),
        .DRDY_I (GTYE4_CHANNEL_DRPRDY_IN),
        .TX_CAL_DONE_I (tx_done),
        .RX_CAL_DONE_I (rx_done)
        );
        endmodule //CPLL_CAL
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v deleted 100755 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        // ***************************
        // * DO NOT MODIFY THIS FILE *
        // ***************************
        `timescale 1ps/1ps
        module gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_rx # (
        parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
        parameter SIM_RESET_SPEEDUP = "TRUE",
        parameter CPLL_CAL_ONLY_TX = 1,
        parameter C_FREERUN_FREQUENCY = 100
        )(
        // control signals
        input wire [17:0] RXOUTCLK_PERIOD_IN,
        input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
        input wire [17:0] CNT_TOL_IN,
        input wire [15:0] FREQ_COUNT_WINDOW_IN,
        // User Interface
        input wire RESET_IN,
        input wire CLK_IN,
        input wire USER_RXPROGDIVRESET_IN,
        output wire USER_RXPRGDIVRESETDONE_OUT,
        output wire USER_RXPMARESETDONE_OUT,
        input wire [2:0] USER_RXOUTCLKSEL_IN,
        input wire USER_RXOUTCLK_BUFG_CE_IN,
        input wire USER_RXOUTCLK_BUFG_CLR_IN,
        output reg USER_CPLLLOCK_OUT,
        input wire USER_GTRXRESET_IN,
        input wire USER_RXCDRHOLD_IN,
        input wire USER_RXPMARESET_IN,
        // Debug Interface
        output wire CPLL_CAL_FAIL,
        output wire CPLL_CAL_DONE,
        output wire [15:0] DEBUG_OUT,
        output wire [17:0] CAL_FREQ_CNT,
        input [3:0] REPEAT_RESET_LIMIT,
        // GT Interface
        input wire GTYE4_RXOUTCLK_IN,
        input wire GTYE4_CPLLLOCK_IN,
        output wire GTYE4_CPLLRESET_OUT,
        output wire GTYE4_CPLLPD_OUT,
        output wire GTYE4_RXPROGDIVRESET_OUT,
        output wire [2:0] GTYE4_RXOUTCLKSEL_OUT,
        input wire GTYE4_RXPRGDIVRESETDONE_IN,
        output wire [9:0] GTYE4_CHANNEL_DRPADDR_OUT,
        output wire [15:0] GTYE4_CHANNEL_DRPDI_OUT,
        output wire GTYE4_CHANNEL_DRPEN_OUT,
        output wire GTYE4_CHANNEL_DRPWE_OUT,
        input wire GTYE4_CHANNEL_DRPRDY_IN,
        input wire [15:0] GTYE4_CHANNEL_DRPDO_IN,
        output wire GTYE4_GTRXRESET_OUT,
        output wire GTYE4_RXPMARESET_OUT,
        output wire GTYE4_RXCDRHOLD_OUT,
        input wire GTYE4_RXPMARESETDONE_IN,
        output wire DONE
        );
        generate if (CPLL_CAL_ONLY_TX == 1)
        begin: gen_cal_rx_dis
        assign GTYE4_RXPROGDIVRESET_OUT = USER_RXPROGDIVRESET_IN;
        assign GTYE4_GTRXRESET_OUT = USER_GTRXRESET_IN;
        assign GTYE4_RXOUTCLKSEL_OUT = USER_RXOUTCLKSEL_IN;
        assign GTYE4_RXCDRHOLD_OUT = USER_RXCDRHOLD_IN;
        assign GTYE4_RXPMARESET_OUT = USER_RXPMARESET_IN;
        assign USER_RXPRGDIVRESETDONE_OUT = GTYE4_RXPRGDIVRESETDONE_IN;
        assign USER_RXPMARESETDONE_OUT = GTYE4_RXPMARESETDONE_IN;
        assign CPLL_CAL_DONE = 1'd0;
        assign CPLL_CAL_FAIL = 1'd0;
        assign DONE = 1'd1;
        assign GTYE4_CHANNEL_DRPEN_OUT = 1'd0;
        assign GTYE4_CHANNEL_DRPWE_OUT = 1'd0;
        assign GTYE4_CPLLPD_OUT = 1'd0;
        assign GTYE4_CPLLRESET_OUT = 1'd0;
        assign DEBUG_OUT = 16'd0;
        assign GTYE4_CHANNEL_DRPDI_OUT = 16'd0;
        assign CAL_FREQ_CNT = 18'd0;
        assign GTYE4_CHANNEL_DRPADDR_OUT = 10'd0;
        always @(posedge CLK_IN) begin
        if(RESET_IN)
        USER_CPLLLOCK_OUT <= 1'b0;
        else
        USER_CPLLLOCK_OUT <= 1'b0;
        end
        end
        else
        begin: gen_cal_rx_en
        //DRP FSM
        localparam DRP_WAIT = 0;
        localparam DRP_READ = 1;
        localparam DRP_READ_ACK = 2;
        localparam DRP_MODIFY = 3;
        localparam DRP_WRITE = 4;
        localparam DRP_WRITE_ACK = 5;
        localparam DRP_DONE = 6;
        localparam RESET = 0;
        localparam READ_X114 = 1;
        localparam CHECK_X114_STATUS = 2;
        localparam READ_PROGDIV_CFG = 3;
        localparam SAVE_PROGDIV_CFG = 4;
        localparam MODIFY_PROGDIV = 5;
        localparam MODIFY_RXOUTCLK_SEL = 6;
        localparam ASSERT_RXCDRHOLD = 7;
        localparam ASSERT_CPLLPD = 8;
        localparam DEASSERT_CPLLPD = 9;
        localparam ASSERT_CPLLRESET = 10;
        localparam DEASSERT_CPLLRESET = 11;
        localparam WAIT_GTCPLLLOCK = 12;
        localparam ASSERT_GTRXRESET = 13;
        localparam WAIT_RXPMARESETDONE = 14;
        localparam WAIT_RXPMARESETDONE_DEASSERT = 15;
        localparam WAIT_RXPMARESETDONE_2 = 16;
        localparam ASSERT_PROGDIVRESET = 17;
        localparam WAIT_PRGDIVRESETDONE = 18;
        localparam CHECK_FREQ = 19;
        localparam RESTORE_READ_X114 = 20;
        localparam RESTORE_PROGDIV = 21;
        localparam CLEAR_FLAG_x114 = 22;
        localparam WAIT_GTCPLLLOCK2 = 23;
        localparam ASSERT_PROGDIVRESET2 = 24;
        localparam WAIT_PRGDIVRESETDONE2= 25;
        localparam CAL_FAIL = 26;
        localparam CAL_DONE = 27;
        reg [31:0] cpll_cal_state = 31'd0;
        wire [4:0] cpll_cal_state_bin;
        reg [6:0] drp_state = 7'd1;
        wire drp_done;
        reg [9:0] daddr = 10'd0;
        reg [15:0] di = 16'd0;
        wire drdy;
        wire [15:0] dout;
        reg den = 1'b0;
        reg dwe = 1'b0;
        reg wr = 1'b0;
        reg rd = 1'b0;
        reg [15:0] di_msk;
        reg [15:0] mask;
        reg [24:0] wait_ctr;
        reg [3:0] repeat_ctr;
        reg [15:0] progdiv_cfg_store = 16'd0;
        reg mask_user_in = 1'b0;
        reg cpllreset_int = 1'b0;
        reg cpllpd_int = 1'b0;
        reg rxprogdivreset_int = 1'b0;
        reg rxcdrhold_int = 1'b0;
        reg gtrxreset_int = 1'b0;
        reg [2:0] rxoutclksel_int = 3'b000;
        reg cal_fail_store = 1'b0;
        reg status_store = 1'b0;
        wire den_i;
        wire dwe_i;
        //All these need to be based on CLK_IN frequency (free_run)
        localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY ); // 1 ms
        localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY ); // 1 ms
        localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY ); // 100 us
        localparam [24:0] SYNTH_WAIT_ASSERT_PROGDIVRESET = C_FREERUN_FREQUENCY ; // 1 us
        localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10;
        localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
        localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;
        localparam [24:0] SIM_WAIT_ASSERT_PROGDIVRESET = SYNTH_WAIT_ASSERT_PROGDIVRESET/10;
        localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
        localparam [4:0] WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
        localparam [24:0] WAIT_ASSERT_CPLLRESET =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
        //pragma translate_on
        SYNTH_WAIT_ASSERT_CPLLRESET;
        localparam [4:0] WAIT_ASSERT_CPLLPD = 5'd25; // >= 100 ns
        localparam [24:0] WAIT_DEASSERT_CPLLRESET =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
        //pragma translate_on
        SYNTH_WAIT_DEASSERT_CPLLRESET;
        localparam [24:0] WAIT_CPLLLOCK =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
        //pragma translate_on
        SYNTH_WAIT_CPLLLOCK;
        localparam [24:0] WAIT_ASSERT_PROGDIVRESET =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_PROGDIVRESET :
        //pragma translate_on
        SYNTH_WAIT_ASSERT_PROGDIVRESET;
        localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
        localparam [2:0] MOD_RXOUTCLK_SEL = 3'b101;
        localparam [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6;
        localparam [9:0] ADDR_X114 = 10'h114;
        // Drive RXOUTCLK with BUFG_GT-buffered source clock, divider = 1
        wire rxoutclkmon;
        //assign rxoutclkmon = GTYE4_RXOUTCLK_IN;
        BUFG_GT bufg_gt_rxoutclkmon_inst (
        .CE (USER_RXOUTCLK_BUFG_CE_IN),
        .CEMASK (1'b1),
        .CLR (USER_RXOUTCLK_BUFG_CLR_IN),
        .CLRMASK (1'b1),
        .DIV (3'b000),
        .I (GTYE4_RXOUTCLK_IN),
        .O (rxoutclkmon)
        );
        wire gtye4_cplllock_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_cplllock_inst (
        .clk_in (CLK_IN),
        .i_in (GTYE4_CPLLLOCK_IN),
        .o_out (gtye4_cplllock_sync)
        );
        wire gtye4_rxpmaresetdone_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxpmaresetdone_inst (
        .clk_in (CLK_IN),
        .i_in (GTYE4_RXPMARESETDONE_IN),
        .o_out (gtye4_rxpmaresetdone_sync)
        );
        wire gtye4_rxprgdivresetdone_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxprgdivresetdone_inst (
        .clk_in (CLK_IN),
        .i_in (GTYE4_RXPRGDIVRESETDONE_IN),
        .o_out (gtye4_rxprgdivresetdone_sync)
        );
        assign GTYE4_CPLLRESET_OUT = cpllreset_int;
        assign GTYE4_CPLLPD_OUT = cpllpd_int;
        always @(posedge CLK_IN) begin
        if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
        USER_CPLLLOCK_OUT <= 1'b0;
        else
        USER_CPLLLOCK_OUT <= gtye4_cplllock_sync;
        end
        assign GTYE4_RXPROGDIVRESET_OUT = mask_user_in ? rxprogdivreset_int : USER_RXPROGDIVRESET_IN;
        assign GTYE4_GTRXRESET_OUT = mask_user_in ? gtrxreset_int : USER_GTRXRESET_IN;
        assign GTYE4_RXOUTCLKSEL_OUT = mask_user_in ? rxoutclksel_int : USER_RXOUTCLKSEL_IN;
        assign GTYE4_RXCDRHOLD_OUT = mask_user_in ? rxcdrhold_int : USER_RXCDRHOLD_IN;
        assign GTYE4_RXPMARESET_OUT = mask_user_in ? 1'b0 : USER_RXPMARESET_IN;
        assign USER_RXPRGDIVRESETDONE_OUT = mask_user_in ? 1'b0 : GTYE4_RXPRGDIVRESETDONE_IN;
        assign USER_RXPMARESETDONE_OUT = mask_user_in ? 1'b0 : GTYE4_RXPMARESETDONE_IN;
        // frequency counter for rxoutclk
        wire [17:0] rxoutclk_freq_cnt;
        reg freq_counter_rst = 1'b1;
        wire freq_cnt_done;
        gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_freq_counter U_RXOUTCLK_FREQ_COUNTER
        (
        .freq_cnt_o(rxoutclk_freq_cnt),
        .done_o(freq_cnt_done),
        .rst_i(freq_counter_rst),
        .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
        .ref_clk_i(CLK_IN),
        .test_clk_i(rxoutclkmon)
        );
        //Debug signals
        assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gtye4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
        assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
        assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
        assign CAL_FREQ_CNT = rxoutclk_freq_cnt;
        assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
        //pragma translate_off
        if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
        begin: gen_sim_cpll_cal_bypass_gtye4
        //CPLL CAL FSM for simulation
        always @(posedge CLK_IN) begin
        if (RESET_IN) begin
        cpll_cal_state <= 0;
        cpll_cal_state[RESET] <= 1'b1;
        cpllreset_int <= 1'b0;
        cpllpd_int <= 1'b0;
        rxprogdivreset_int <= 1'b0;
        mask_user_in <= 1'b0;
        wr <= 1'b0;
        rd <= 1'b0;
        rxcdrhold_int <= 1'b0;
        gtrxreset_int <= 1'b0;
        end
        else begin
        cpll_cal_state <= 0;
        case(1'b1) // synthesis parallel_case full_case
        cpll_cal_state[RESET]:
        begin
        wait_ctr <= 25'd0;
        repeat_ctr <= 4'd0;
        mask_user_in <= 1'b1;
        di_msk <= 16'b0000_0000_0000_0000;
        cpll_cal_state[READ_X114] <= 1'b1;
        end
        cpll_cal_state[READ_X114]:
        begin
        mask_user_in <= 1'b1;
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
        end
        else
        cpll_cal_state[READ_X114] <= 1'b1;
        end
        cpll_cal_state[CHECK_X114_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        else
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        cpll_cal_state[READ_PROGDIV_CFG]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= {1'b1,dout[14:0]};
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGDIV_CFG]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[MODIFY_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        di_msk<= MOD_PROGDIV_CFG;
        end
        cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
        begin
        cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
        end
        cpll_cal_state[ASSERT_RXCDRHOLD]:
        begin
        rxcdrhold_int <= 1'b1;
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        end
        cpll_cal_state[ASSERT_CPLLRESET]:
        begin
        cpllreset_int <= 1'b1;
        freq_counter_rst <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        cpll_cal_state[DEASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[WAIT_GTCPLLLOCK]:
        begin
        if(!gtye4_cplllock_sync) begin
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        end
        else begin
        cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
        end
        end
        cpll_cal_state[ASSERT_GTRXRESET]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        gtrxreset_int <= 1'b1;
        cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
        end
        else begin
        gtrxreset_int <= 1'b0;
        cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE]:
        begin
        if (gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
        begin
        if (!gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE_2]:
        begin
        if (gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
        end
        end
        cpll_cal_state[ASSERT_PROGDIVRESET]:
        begin
        if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        rxprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        end
        else begin
        rxprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE]:
        begin
        if (gtye4_rxprgdivresetdone_sync) begin
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        freq_counter_rst <= 1'b0;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        end
        end
        cpll_cal_state[CHECK_FREQ]:
        begin
        if(freq_cnt_done) begin
        if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        cal_fail_store <= 1'b0;
        end
        else begin
        if (repeat_ctr < REPEAT_RESET_LIMIT) begin
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        repeat_ctr <= repeat_ctr + 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        cal_fail_store <= 1'b1;
        end
        end
        end
        else
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        end
        cpll_cal_state[RESTORE_READ_X114]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= dout;
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[CLEAR_FLAG_x114]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[WAIT_GTCPLLLOCK2]:
        begin
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        if(!gtye4_cplllock_sync)
        cal_fail_store <= 1'b1;
        else
        cal_fail_store <= cal_fail_store;
        end
        cpll_cal_state[ASSERT_PROGDIVRESET2]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        rxprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        end
        else begin
        rxprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
        begin
        if (gtye4_rxprgdivresetdone_sync) begin
        if (cal_fail_store)
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        else
        cpll_cal_state[CAL_DONE] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        end
        end
        cpll_cal_state[CAL_FAIL]:
        begin
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        cpll_cal_state[CAL_DONE]:
        begin
        cpll_cal_state[CAL_DONE] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        endcase
        end
        end // always block
        end
        else
        begin: gen_cpll_cal_gtye4_rx
        //pragma translate_on
        //CPLL CAL FSM
        always @(posedge CLK_IN) begin
        if (RESET_IN) begin
        cpll_cal_state <= 0;
        cpll_cal_state[RESET] <= 1'b1;
        cpllreset_int <= 1'b0;
        cpllpd_int <= 1'b0;
        rxprogdivreset_int <= 1'b0;
        mask_user_in <= 1'b0;
        wr <= 1'b0;
        rd <= 1'b0;
        rxcdrhold_int <= 1'b0;
        gtrxreset_int <= 1'b0;
        end
        else begin
        cpll_cal_state <= 0;
        case(1'b1) // synthesis parallel_case full_case
        cpll_cal_state[RESET]:
        begin
        wait_ctr <= 25'd0;
        repeat_ctr <= 4'd0;
        mask_user_in <= 1'b1;
        di_msk <= 16'b0000_0000_0000_0000;
        cpll_cal_state[READ_X114] <= 1'b1;
        end
        cpll_cal_state[READ_X114]:
        begin
        mask_user_in <= 1'b1;
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
        end
        else
        cpll_cal_state[READ_X114] <= 1'b1;
        end
        cpll_cal_state[CHECK_X114_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        else
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        cpll_cal_state[READ_PROGDIV_CFG]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= {1'b1,dout[14:0]};
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGDIV_CFG]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[MODIFY_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        di_msk<= MOD_PROGDIV_CFG;
        end
        cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
        begin
        cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
        end
        cpll_cal_state[ASSERT_RXCDRHOLD]:
        begin
        rxcdrhold_int <= 1'b1;
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        end
        cpll_cal_state[ASSERT_CPLLPD]:
        begin
        if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        end
        else begin
        cpllpd_int <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[DEASSERT_CPLLPD]:
        begin
        if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
        end
        else begin
        cpllpd_int <= 1'b0;
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 16'd0;
        freq_counter_rst <= 1'b1;
        end
        end
        cpll_cal_state[ASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b1;
        freq_counter_rst <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[DEASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[WAIT_GTCPLLLOCK]:
        begin
        if(wait_ctr < WAIT_CPLLLOCK) begin
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= wait_ctr + 1'b1;
        end
        else begin
        cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[ASSERT_GTRXRESET]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        gtrxreset_int <= 1'b1;
        cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
        end
        else begin
        gtrxreset_int <= 1'b0;
        cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE]:
        begin
        if (gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
        begin
        if (!gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
        end
        end
        cpll_cal_state[WAIT_RXPMARESETDONE_2]:
        begin
        if (gtye4_rxpmaresetdone_sync) begin
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
        end
        end
        cpll_cal_state[ASSERT_PROGDIVRESET]:
        begin
        if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        rxprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        end
        else begin
        rxprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE]:
        begin
        if (gtye4_rxprgdivresetdone_sync) begin
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        freq_counter_rst <= 1'b0;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        end
        end
        cpll_cal_state[CHECK_FREQ]:
        begin
        if(freq_cnt_done) begin
        if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        cal_fail_store <= 1'b0;
        end
        else begin
        if (repeat_ctr < REPEAT_RESET_LIMIT) begin
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        repeat_ctr <= repeat_ctr + 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        cal_fail_store <= 1'b1;
        end
        end
        end
        else
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        end
        cpll_cal_state[RESTORE_READ_X114]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= dout;
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[CLEAR_FLAG_x114]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[WAIT_GTCPLLLOCK2]:
        begin
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        if(!gtye4_cplllock_sync)
        cal_fail_store <= 1'b1;
        else
        cal_fail_store <= cal_fail_store;
        end
        cpll_cal_state[ASSERT_PROGDIVRESET2]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        rxprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        end
        else begin
        rxprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
        begin
        if (gtye4_rxprgdivresetdone_sync) begin
        if (cal_fail_store)
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        else
        cpll_cal_state[CAL_DONE] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        end
        end
        cpll_cal_state[CAL_FAIL]:
        begin
        rxcdrhold_int <= 1'b0;
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        cpll_cal_state[CAL_DONE]:
        begin
        rxcdrhold_int <= 1'b0;
        cpll_cal_state[CAL_DONE] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        endcase
        end
        end // always block
        //pragma translate_off
        end
        //pragma translate_on
        always @(posedge CLK_IN) begin
        if (cpll_cal_state[RESET])
        rxoutclksel_int <= 3'b0;
        else if (cpll_cal_state[MODIFY_RXOUTCLK_SEL])
        rxoutclksel_int <= MOD_RXOUTCLK_SEL;
        else
        rxoutclksel_int <= rxoutclksel_int;
        end
        always @(posedge CLK_IN) begin
        if (cpll_cal_state[RESET]) begin
        daddr <= 10'h000;
        mask <= 16'b1111_1111_1111_1111;
        end
        else if (cpll_cal_state[READ_X114] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X114] | cpll_cal_state[CLEAR_FLAG_x114]) begin
        daddr <= ADDR_X114;
        end
        else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
        daddr <= ADDR_RX_PROGDIV_CFG;
        end
        end
        assign drp_done = drp_state[DRP_DONE];
        assign GTYE4_CHANNEL_DRPEN_OUT = den;
        assign GTYE4_CHANNEL_DRPWE_OUT = dwe;
        assign GTYE4_CHANNEL_DRPADDR_OUT = daddr;
        assign GTYE4_CHANNEL_DRPDI_OUT = di;
        assign drdy = GTYE4_CHANNEL_DRPRDY_IN;
        assign dout = GTYE4_CHANNEL_DRPDO_IN;
        always @(posedge CLK_IN) begin
        if (RESET_IN) begin
        den <= 1'b0;
        dwe <= 1'b0;
        di <= 16'h0000;
        drp_state <= 0;
        drp_state[DRP_WAIT] <= 1'b1;
        end
        else begin
        drp_state <= 0;
        case (1'b1) // synthesis parallel_case full_case
        drp_state[DRP_WAIT]:
        begin
        if (rd) drp_state[DRP_READ] <= 1'b1;
        else if (wr) drp_state[DRP_WRITE] <= 1'b1;
        else drp_state[DRP_WAIT] <= 1'b1;
        end
        drp_state[DRP_READ]:
        begin
        den <= 1'b1;
        drp_state[DRP_READ_ACK] <= 1'b1;
        end
        drp_state[DRP_READ_ACK]:
        begin
        den <= 1'b0;
        if (drdy == 1'b1) begin
        if (rd) drp_state[DRP_DONE] <= 1'b1;
        else drp_state[DRP_MODIFY] <= 1'b1;
        end
        else drp_state[DRP_READ_ACK] <= 1'b1;
        end
        drp_state[DRP_MODIFY]:
        begin
        drp_state[DRP_WRITE] <= 1'b1;
        end
        drp_state[DRP_WRITE]:
        begin
        den <= 1'b1;
        dwe <= 1'b1;
        di <= di_msk;
        drp_state[DRP_WRITE_ACK] <= 1'b1;
        end
        drp_state[DRP_WRITE_ACK]:
        begin
        den <= 1'b0;
        dwe <= 1'b0;
        if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
        else drp_state[DRP_WRITE_ACK] <= 1'b1;
        end
        drp_state[DRP_DONE]:
        begin
        drp_state[DRP_WAIT] <= 1'b1;
        end
        endcase
        end
        end
        //debug logic - convert one hot state to binary
        genvar i,j;
        for (j=0; j<5; j=j+1)
        begin : jl
        wire [32-1:0] tmp_mask;
        for (i=0; i<32; i=i+1)
        begin : il
        assign tmp_mask[i] = i[j];
        end
        assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
        end
        end
        endgenerate
        endmodule //CPLL_CAL
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v deleted 100755 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
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        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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        // including negligence, or under any other theory of
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        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
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        // by a third party) even if such damage or loss was
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        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        // ***************************
        // * DO NOT MODIFY THIS FILE *
        // ***************************
        `timescale 1ps/1ps
        module gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx # (
        parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
        parameter SIM_RESET_SPEEDUP = "TRUE",
        parameter C_FREERUN_FREQUENCY = 100,
        parameter REVISION = 2,
        parameter C_PCIE_ENABLE = "FALSE",
        parameter C_PCIE_CORECLK_FREQ = 250
        )(
        // control signals
        input wire [17:0] TXOUTCLK_PERIOD_IN,
        input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
        input wire [17:0] CNT_TOL_IN,
        input wire [15:0] FREQ_COUNT_WINDOW_IN,
        // User Interface
        input wire RESET_IN,
        input wire CLK_IN,
        input wire [1:0] USER_TXPLLCLKSEL,
        input wire USER_TXPROGDIVRESET_IN,
        output reg USER_TXPRGDIVRESETDONE_OUT,
        input wire [2:0] USER_TXOUTCLKSEL_IN,
        input wire USER_TXOUTCLK_BUFG_CE_IN,
        input wire USER_TXOUTCLK_BUFG_CLR_IN,
        output reg USER_CPLLLOCK_OUT,
        // Debug Interface
        output wire CPLL_CAL_FAIL,
        output wire CPLL_CAL_DONE,
        output wire [15:0] DEBUG_OUT,
        output wire [17:0] CAL_FREQ_CNT,
        input [3:0] REPEAT_RESET_LIMIT,
        // GT Interface
        input wire GTYE4_TXOUTCLK_IN,
        input wire GTYE4_CPLLLOCK_IN,
        output wire GTYE4_CPLLRESET_OUT,
        output wire GTYE4_CPLLPD_OUT,
        output reg GTYE4_TXPROGDIVRESET_OUT,
        output reg [2:0] GTYE4_TXOUTCLKSEL_OUT,
        input wire GTYE4_TXPRGDIVRESETDONE_IN,
        output wire [9:0] GTYE4_CHANNEL_DRPADDR_OUT,
        output wire [15:0] GTYE4_CHANNEL_DRPDI_OUT,
        output wire GTYE4_CHANNEL_DRPEN_OUT,
        output wire GTYE4_CHANNEL_DRPWE_OUT,
        input wire GTYE4_CHANNEL_DRPRDY_IN,
        input wire [15:0] GTYE4_CHANNEL_DRPDO_IN,
        output wire DONE
        );
        //DRP FSM
        localparam DRP_WAIT = 0;
        localparam DRP_READ = 1;
        localparam DRP_READ_ACK = 2;
        localparam DRP_MODIFY = 3;
        localparam DRP_WRITE = 4;
        localparam DRP_WRITE_ACK = 5;
        localparam DRP_DONE = 6;
        localparam RESET = 0;
        localparam READ_X0E1 = 1;
        localparam CHECK_X0E1_STATUS = 2;
        localparam READ_PROGCLK_SEL = 3;
        localparam SAVE_PROGCLK_SEL = 4;
        localparam READ_X079 = 5;
        localparam CHECK_X079_STATUS = 6;
        localparam READ_PROGDIV_CFG = 7;
        localparam SAVE_PROGDIV_CFG = 8;
        localparam READ_X0E1_BEFORE_PROGCLK_SEL_MOD = 9;
        localparam MODIFY_PROGCLK_SEL = 10;
        localparam MODIFY_PROGDIV = 11;
        localparam MODIFY_TXOUTCLK_SEL = 12;
        localparam ASSERT_CPLLPD = 13;
        localparam DEASSERT_CPLLPD = 14;
        localparam ASSERT_CPLLRESET = 15;
        localparam DEASSERT_CPLLRESET = 16;
        localparam WAIT_GTCPLLLOCK = 17;
        localparam ASSERT_PROGDIVRESET = 18;
        localparam WAIT_PRGDIVRESETDONE = 19;
        localparam CHECK_FREQ = 20;
        localparam RESTORE_READ_X0E1 = 21;
        localparam RESTORE_READ_X079 = 22;
        localparam RESTORE_PROGDIV = 23;
        localparam RESTORE_PROGCLK_SEL = 24;
        localparam CLEAR_FLAG_x0E1 = 25;
        localparam CLEAR_FLAG_x079 = 26;
        localparam WAIT_GTCPLLLOCK2 = 27;
        localparam ASSERT_PROGDIVRESET2 = 28;
        localparam WAIT_PRGDIVRESETDONE2= 29;
        localparam CAL_FAIL = 30;
        localparam CAL_DONE = 31;
        reg [31:0] cpll_cal_state = 31'd0;
        wire [4:0] cpll_cal_state_bin;
        reg [6:0] drp_state = 7'd1;
        wire drp_done;
        reg [9:0] daddr = 10'd0;
        reg [15:0] di = 16'd0;
        wire drdy;
        wire [15:0] dout;
        reg den = 1'b0;
        reg dwe = 1'b0;
        reg wr = 1'b0;
        reg rd = 1'b0;
        reg [15:0] di_msk;
        reg [15:0] mask;
        reg [24:0] wait_ctr;
        reg [3:0] repeat_ctr;
        reg [15:0] progclk_sel_store = 16'd0;
        reg [15:0] progdiv_cfg_store = 16'd0;
        reg fboost_store = 1'b0;
        reg mask_user_in = 1'b0;
        reg cpllreset_int = 1'b0;
        reg cpllpd_int = 1'b0;
        reg txprogdivreset_int = 1'b0;
        reg [2:0] txoutclksel_int = 3'b000;
        reg cal_fail_store = 1'b0;
        reg [15:0] x0e1_store = 16'd0;
        reg status_store = 1'b0;
        wire den_i;
        wire dwe_i;
        //All these need to be based on CLK_IN frequency (free_run)
        localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY); // 1 ms
        localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY); // 1 ms
        localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY); // 100 us
        localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10;
        localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
        localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;
        localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
        localparam [4:0] WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
        localparam [24:0] WAIT_ASSERT_CPLLRESET =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
        //pragma translate_on
        SYNTH_WAIT_ASSERT_CPLLRESET;
        localparam [4:0] WAIT_ASSERT_CPLLPD = 5'd25; // >= 100 ns
        localparam [24:0] WAIT_DEASSERT_CPLLRESET =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
        //pragma translate_on
        SYNTH_WAIT_DEASSERT_CPLLRESET;
        localparam [24:0] WAIT_CPLLLOCK =
        //pragma translate_off
        (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
        //pragma translate_on
        SYNTH_WAIT_CPLLLOCK;
        localparam [1:0] MOD_PROGCLK_SEL = 2'b10;
        localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
        localparam [2:0] MOD_TXOUTCLK_SEL = 3'b101;
        localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
        localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h057; //GTY /GTH addresses are different (003E in GTH; 0057 in GTY)
        localparam [9:0] ADDR_X0E1 = 10'h0E1;
        localparam [9:0] ADDR_X079 = 10'h079;
        // Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
        wire txoutclkmon;
        //assign txoutclkmon = GTYE4_TXOUTCLK_IN;
        BUFG_GT bufg_gt_txoutclkmon_inst (
        .CE (USER_TXOUTCLK_BUFG_CE_IN),
        .CEMASK (1'b1),
        .CLR (USER_TXOUTCLK_BUFG_CLR_IN),
        .CLRMASK (1'b1),
        .DIV (3'b000),
        .I (GTYE4_TXOUTCLK_IN),
        .O (txoutclkmon)
        );
        wire gtye4_cplllock_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_cplllock_inst (
        .clk_in (CLK_IN),
        .i_in (GTYE4_CPLLLOCK_IN),
        .o_out (gtye4_cplllock_sync)
        );
        wire user_txprogdivreset_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
        .clk_in (CLK_IN),
        .i_in (USER_TXPROGDIVRESET_IN),
        .o_out (user_txprogdivreset_sync)
        );
        wire gtye4_txprgdivresetdone_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
        .clk_in (CLK_IN),
        .i_in (GTYE4_TXPRGDIVRESETDONE_IN),
        .o_out (gtye4_txprgdivresetdone_sync)
        );
        wire [2:0] user_txoutclksel_sync;
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
        .clk_in (CLK_IN),
        .i_in (USER_TXOUTCLKSEL_IN[0]),
        .o_out (user_txoutclksel_sync[0])
        );
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
        .clk_in (CLK_IN),
        .i_in (USER_TXOUTCLKSEL_IN[1]),
        .o_out (user_txoutclksel_sync[1])
        );
        gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
        .clk_in (CLK_IN),
        .i_in (USER_TXOUTCLKSEL_IN[2]),
        .o_out (user_txoutclksel_sync[2])
        );
        assign GTYE4_CPLLRESET_OUT = cpllreset_int;
        assign GTYE4_CPLLPD_OUT = cpllpd_int;
        always @(posedge CLK_IN) begin
        if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
        USER_CPLLLOCK_OUT <= 1'b0;
        else
        USER_CPLLLOCK_OUT <= gtye4_cplllock_sync;
        end
        generate if (C_PCIE_ENABLE)
        begin : pcie_txoutclksel
        always @(*) begin
        GTYE4_TXOUTCLKSEL_OUT <= mask_user_in ? txoutclksel_int : USER_TXOUTCLKSEL_IN;
        GTYE4_TXPROGDIVRESET_OUT <= mask_user_in ? txprogdivreset_int : USER_TXPROGDIVRESET_IN;
        end
        end
        else begin : non_pcie_txoutclksel
        always @(posedge CLK_IN) begin
        if (mask_user_in)
        GTYE4_TXPROGDIVRESET_OUT <= txprogdivreset_int;
        else
        GTYE4_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
        end
        always @(posedge CLK_IN) begin
        if (mask_user_in)
        GTYE4_TXOUTCLKSEL_OUT <= txoutclksel_int;
        else
        GTYE4_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
        end
        end
        endgenerate
        always @(posedge CLK_IN) begin
        if (mask_user_in)
        USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
        else
        USER_TXPRGDIVRESETDONE_OUT <= gtye4_txprgdivresetdone_sync;
        end
        // frequency counter for txoutclk
        wire [17:0] txoutclk_freq_cnt;
        reg freq_counter_rst = 1'b1;
        wire freq_cnt_done;
        gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
        (
        .freq_cnt_o(txoutclk_freq_cnt),
        .done_o(freq_cnt_done),
        .rst_i(freq_counter_rst),
        .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
        .ref_clk_i(CLK_IN),
        .test_clk_i(txoutclkmon)
        );
        //Debug signals
        assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gtye4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
        assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
        assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
        assign CAL_FREQ_CNT = txoutclk_freq_cnt;
        assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
        //pragma translate_off
        generate if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
        begin: gen_sim_cpll_cal_bypass_gtye4
        //CPLL CAL FSM for simulation
        always @(posedge CLK_IN) begin
        if (RESET_IN) begin
        cpll_cal_state <= 0;
        cpll_cal_state[RESET] <= 1'b1;
        cpllreset_int <= 1'b0;
        cpllpd_int <= 1'b0;
        txprogdivreset_int <= 1'b0;
        mask_user_in <= 1'b0;
        wr <= 1'b0;
        rd <= 1'b0;
        end
        else begin
        cpll_cal_state <= 0;
        case(1'b1) // synthesis parallel_case full_case
        cpll_cal_state[RESET]:
        begin
        wait_ctr <= 25'd0;
        repeat_ctr <= 4'd0;
        mask_user_in <= 1'b1;
        di_msk <= 16'b0000_0000_0000_0000;
        cpll_cal_state[READ_X0E1] <= 1'b1;
        end
        cpll_cal_state[READ_X0E1]:
        begin
        mask_user_in <= 1'b1;
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
        end
        else
        cpll_cal_state[READ_X0E1] <= 1'b1;
        end
        cpll_cal_state[CHECK_X0E1_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[READ_X079] <= 1'b1;
        else
        cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
        end
        cpll_cal_state[READ_PROGCLK_SEL]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progclk_sel_store <= dout;
        cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[READ_X079] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
        end
        di_msk <= {1'b1,progclk_sel_store[14:0]};
        end
        cpll_cal_state[READ_X079]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_X079] <= 1'b1;
        end
        end
        cpll_cal_state[CHECK_X079_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        else
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        cpll_cal_state[READ_PROGDIV_CFG]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= {1'b1,dout[14:0]};
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGDIV_CFG]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        x0e1_store <= dout;
        cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        end
        end
        cpll_cal_state[MODIFY_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
        end
        di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
        end
        cpll_cal_state[MODIFY_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        di_msk<= MOD_PROGDIV_CFG;
        end
        cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
        begin
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        end
        cpll_cal_state[ASSERT_CPLLRESET]:
        begin
        cpllreset_int <= 1'b1;
        freq_counter_rst <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        cpll_cal_state[DEASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[WAIT_GTCPLLLOCK]:
        begin
        if(!gtye4_cplllock_sync) begin
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_READ_X0E1]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progclk_sel_store <= dout;
        cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_READ_X079]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= dout;
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end
        di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
        end
        cpll_cal_state[RESTORE_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
        end
        di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
        end
        cpll_cal_state[CLEAR_FLAG_x0E1]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[CLEAR_FLAG_x079]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[WAIT_GTCPLLLOCK2]:
        begin
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        if(!gtye4_cplllock_sync)
        cal_fail_store <= 1'b1;
        else
        cal_fail_store <= cal_fail_store;
        end
        cpll_cal_state[ASSERT_PROGDIVRESET2]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        txprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        end
        else begin
        txprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
        begin
        if (gtye4_txprgdivresetdone_sync) begin
        if (cal_fail_store)
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        else
        cpll_cal_state[CAL_DONE] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        end
        end
        cpll_cal_state[CAL_FAIL]:
        begin
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        cpll_cal_state[CAL_DONE]:
        begin
        cpll_cal_state[CAL_DONE] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        endcase
        end
        end // always block
        end
        else
        begin: gen_cpll_cal_gtye4
        //pragma translate_on
        //CPLL CAL FSM
        always @(posedge CLK_IN) begin
        if (RESET_IN) begin
        cpll_cal_state <= 0;
        cpll_cal_state[RESET] <= 1'b1;
        cpllreset_int <= 1'b0;
        cpllpd_int <= 1'b0;
        txprogdivreset_int <= 1'b0;
        mask_user_in <= 1'b0;
        wr <= 1'b0;
        rd <= 1'b0;
        end
        else begin
        cpll_cal_state <= 0;
        case(1'b1) // synthesis parallel_case full_case
        cpll_cal_state[RESET]:
        begin
        wait_ctr <= 25'd0;
        repeat_ctr <= 4'd0;
        mask_user_in <= 1'b1;
        di_msk <= 16'b0000_0000_0000_0000;
        cpll_cal_state[READ_X0E1] <= 1'b1;
        end
        cpll_cal_state[READ_X0E1]:
        begin
        mask_user_in <= 1'b1;
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
        end
        else
        cpll_cal_state[READ_X0E1] <= 1'b1;
        end
        cpll_cal_state[CHECK_X0E1_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[READ_X079] <= 1'b1;
        else
        cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
        end
        cpll_cal_state[READ_PROGCLK_SEL]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progclk_sel_store <= dout;
        cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[READ_X079] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
        end
        di_msk <= {1'b1,progclk_sel_store[14:0]};
        end
        cpll_cal_state[READ_X079]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        status_store <= dout[15];
        cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_X079] <= 1'b1;
        end
        end
        cpll_cal_state[CHECK_X079_STATUS]:
        begin
        if (status_store)
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        else
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        cpll_cal_state[READ_PROGDIV_CFG]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= {1'b1,dout[14:0]};
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
        end
        end
        cpll_cal_state[SAVE_PROGDIV_CFG]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        end
        else begin
        cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
        end
        di_msk <= progdiv_cfg_store;
        end
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        x0e1_store <= dout;
        cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
        end
        end
        cpll_cal_state[MODIFY_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
        end
        di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
        end
        cpll_cal_state[MODIFY_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        di_msk<= MOD_PROGDIV_CFG;
        end
        cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
        begin
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        end
        cpll_cal_state[ASSERT_CPLLPD]:
        begin
        if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        end
        else begin
        cpllpd_int <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[DEASSERT_CPLLPD]:
        begin
        if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
        end
        else begin
        cpllpd_int <= 1'b0;
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 16'd0;
        freq_counter_rst <= 1'b1;
        end
        end
        cpll_cal_state[ASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b1;
        freq_counter_rst <= 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[DEASSERT_CPLLRESET]:
        begin
        if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
        end
        else begin
        cpllreset_int <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[WAIT_GTCPLLLOCK]:
        begin
        if(wait_ctr < WAIT_CPLLLOCK) begin
        cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
        wait_ctr <= wait_ctr + 1'b1;
        end
        else begin
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        wait_ctr <= 16'd0;
        end
        end
        cpll_cal_state[ASSERT_PROGDIVRESET]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        txprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
        end
        else begin
        txprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE]:
        begin
        if (gtye4_txprgdivresetdone_sync) begin
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        freq_counter_rst <= 1'b0;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
        end
        end
        cpll_cal_state[CHECK_FREQ]:
        begin
        if(freq_cnt_done) begin
        if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
        cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
        cal_fail_store <= 1'b0;
        end
        else begin
        if (repeat_ctr < REPEAT_RESET_LIMIT) begin
        cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
        repeat_ctr <= repeat_ctr + 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
        cal_fail_store <= 1'b1;
        end
        end
        end
        else
        cpll_cal_state[CHECK_FREQ] <= 1'b1;
        end
        cpll_cal_state[RESTORE_READ_X0E1]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progclk_sel_store <= dout;
        cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_READ_X079]:
        begin
        rd <= 1'b1;
        if (drp_done) begin
        rd <= 1'b0;
        progdiv_cfg_store <= dout;
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end else begin
        cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
        end
        end
        cpll_cal_state[RESTORE_PROGDIV]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
        end
        di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
        end
        cpll_cal_state[RESTORE_PROGCLK_SEL]:
        begin
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
        end
        else begin
        cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
        end
        di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
        end
        cpll_cal_state[CLEAR_FLAG_x0E1]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[CLEAR_FLAG_x079]:
        begin
        //set [15] to 0
        wr <= 1'b1;
        if (drp_done) begin
        wr <= 1'b0;
        cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
        end
        else begin
        cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
        end
        // clear
        di_msk <= 16'h0000;
        end
        cpll_cal_state[WAIT_GTCPLLLOCK2]:
        begin
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        if(!gtye4_cplllock_sync)
        cal_fail_store <= 1'b1;
        else
        cal_fail_store <= cal_fail_store;
        end
        cpll_cal_state[ASSERT_PROGDIVRESET2]:
        begin
        if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
        wait_ctr <= wait_ctr + 1'b1;
        txprogdivreset_int <= 1'b1;
        cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
        end
        else begin
        txprogdivreset_int <= 1'b0;
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        wait_ctr <= 25'd0;
        end
        end
        cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
        begin
        if (gtye4_txprgdivresetdone_sync) begin
        if (cal_fail_store)
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        else
        cpll_cal_state[CAL_DONE] <= 1'b1;
        end
        else begin
        cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
        end
        end
        cpll_cal_state[CAL_FAIL]:
        begin
        cpll_cal_state[CAL_FAIL] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        cpll_cal_state[CAL_DONE]:
        begin
        cpll_cal_state[CAL_DONE] <= 1'b1;
        mask_user_in <= 1'b0;
        end
        endcase
        end
        end // always block
        //pragma translate_off
        end
        endgenerate
        //pragma translate_on
        always @(posedge CLK_IN) begin
        if (cpll_cal_state[RESET])
        txoutclksel_int <= 3'b0;
        else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
        txoutclksel_int <= MOD_TXOUTCLK_SEL;
        end
        always @(posedge CLK_IN) begin
        if (cpll_cal_state[RESET]) begin
        daddr <= 10'h000;
        mask <= 16'b1111_1111_1111_1111;
        end
        else if (cpll_cal_state[READ_X0E1] | cpll_cal_state[SAVE_PROGCLK_SEL] | cpll_cal_state[RESTORE_READ_X0E1] | cpll_cal_state[CLEAR_FLAG_x0E1] | cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]) begin
        daddr <= ADDR_X0E1;
        end
        else if (cpll_cal_state[READ_X079] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X079] | cpll_cal_state[CLEAR_FLAG_x079]) begin
        daddr <= ADDR_X079;
        end
        else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
        daddr <= ADDR_TX_PROGCLK_SEL;
        end
        else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
        daddr <= ADDR_TX_PROGDIV_CFG;
        end
        end
        assign drp_done = drp_state[DRP_DONE];
        assign GTYE4_CHANNEL_DRPEN_OUT = den;
        assign GTYE4_CHANNEL_DRPWE_OUT = dwe;
        assign GTYE4_CHANNEL_DRPADDR_OUT = daddr;
        assign GTYE4_CHANNEL_DRPDI_OUT = di;
        assign drdy = GTYE4_CHANNEL_DRPRDY_IN;
        assign dout = GTYE4_CHANNEL_DRPDO_IN;
        always @(posedge CLK_IN or posedge RESET_IN) begin
        if (RESET_IN) begin
        den <= 1'b0;
        dwe <= 1'b0;
        di <= 16'h0000;
        drp_state <= 0;
        drp_state[DRP_WAIT] <= 1'b1;
        end
        else begin
        drp_state <= 0;
        case (1'b1) // synthesis parallel_case full_case
        drp_state[DRP_WAIT]:
        begin
        if (rd) drp_state[DRP_READ] <= 1'b1;
        else if (wr) drp_state[DRP_WRITE] <= 1'b1;
        else drp_state[DRP_WAIT] <= 1'b1;
        end
        drp_state[DRP_READ]:
        begin
        den <= 1'b1;
        drp_state[DRP_READ_ACK] <= 1'b1;
        end
        drp_state[DRP_READ_ACK]:
        begin
        den <= 1'b0;
        if (drdy == 1'b1) begin
        if (rd) drp_state[DRP_DONE] <= 1'b1;
        else drp_state[DRP_MODIFY] <= 1'b1;
        end
        else drp_state[DRP_READ_ACK] <= 1'b1;
        end
        drp_state[DRP_MODIFY]:
        begin
        drp_state[DRP_WRITE] <= 1'b1;
        end
        drp_state[DRP_WRITE]:
        begin
        den <= 1'b1;
        dwe <= 1'b1;
        di <= di_msk;
        drp_state[DRP_WRITE_ACK] <= 1'b1;
        end
        drp_state[DRP_WRITE_ACK]:
        begin
        den <= 1'b0;
        dwe <= 1'b0;
        if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
        else drp_state[DRP_WRITE_ACK] <= 1'b1;
        end
        drp_state[DRP_DONE]:
        begin
        drp_state[DRP_WAIT] <= 1'b1;
        end
        endcase
        end
        end
        //debug logic - convert one hot state to binary
        genvar i,j;
        generate
        for (j=0; j<5; j=j+1)
        begin : jl
        wire [32-1:0] tmp_mask;
        for (i=0; i<32; i=i+1)
        begin : il
        assign tmp_mask[i] = i[j];
        end
        assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
        end
        endgenerate
        endmodule //CPLL_CAL
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v deleted 100755 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        // ***************************
        // * DO NOT MODIFY THIS FILE *
        // ***************************
        `timescale 1ps/1ps
        module gtwizard_ultrascale_v1_7_7_gtye4_delay_powergood # (
        parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
        parameter C_PCIE_ENABLE = "FALSE"
        )(
        input wire GT_TXOUTCLKPCS,
        input wire GT_GTPOWERGOOD,
        input wire [2:0] USER_TXRATE,
        input wire USER_TXRATEMODE,
        input wire USER_GTTXRESET,
        input wire USER_TXPMARESET,
        input wire USER_TXPISOPD,
        output wire USER_GTPOWERGOOD,
        output wire [2:0] GT_TXRATE,
        output wire GT_TXRATEMODE,
        output wire GT_GTTXRESET,
        output wire GT_TXPMARESET,
        output wire GT_TXPISOPD
        );
        generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
        begin : gen_powergood_nodelay
        assign GT_TXPISOPD = USER_TXPISOPD;
        assign GT_GTTXRESET = USER_GTTXRESET;
        assign GT_TXPMARESET = USER_TXPMARESET;
        assign GT_TXRATE = USER_TXRATE;
        assign GT_TXRATEMODE = USER_TXRATEMODE;
        assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
        end
        else
        begin: gen_powergood_delay
        (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
        (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] wait_cnt;
        (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
        (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
        wire intclk_rrst_n;
        //--------------------------------------------------------------------------
        // POWER ON FSM Encoding
        //--------------------------------------------------------------------------
        localparam PWR_ON_WAIT_CNT = 4'd0;
        localparam PWR_ON_DONE = 4'd1;
        //--------------------------------------------------------------------------------------------------
        // Reset Synchronizer
        //--------------------------------------------------------------------------------------------------
        always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
        begin
        if (!GT_GTPOWERGOOD)
        intclk_rrst_n_r <= 5'd0;
        else if(!int_pwr_on_fsm)
        intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1};
        end
        assign intclk_rrst_n = intclk_rrst_n_r[4];
        //--------------------------------------------------------------------------------------------------
        // Wait counter
        //--------------------------------------------------------------------------------------------------
        always @ (posedge GT_TXOUTCLKPCS)
        begin
        if (!intclk_rrst_n)
        wait_cnt <= 9'd0;
        else begin
        if (int_pwr_on_fsm == PWR_ON_WAIT_CNT)
        wait_cnt <= {wait_cnt[7:0],1'b1};
        else
        wait_cnt <= wait_cnt;
        end
        end
        //--------------------------------------------------------------------------------------------------
        // Power On FSM
        //--------------------------------------------------------------------------------------------------
        always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
        begin
        if (!GT_GTPOWERGOOD)
        begin
        int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
        end
        else begin
        case (int_pwr_on_fsm)
        PWR_ON_WAIT_CNT :
        begin
        int_pwr_on_fsm <= (wait_cnt[7] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
        end
        PWR_ON_DONE :
        begin
        int_pwr_on_fsm <= PWR_ON_DONE;
        end
        default :
        begin
        int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
        end
        endcase
        end
        end
        always @(posedge GT_TXOUTCLKPCS)
        pwr_on_fsm <= int_pwr_on_fsm;
        assign GT_TXPISOPD = pwr_on_fsm ? USER_TXPISOPD : 1'b1;
        assign GT_GTTXRESET = pwr_on_fsm ? USER_GTTXRESET : !GT_GTPOWERGOOD;
        assign GT_TXPMARESET = pwr_on_fsm ? USER_TXPMARESET : 1'b0;
        assign GT_TXRATE = pwr_on_fsm ? USER_TXRATE : 3'b001;
        assign GT_TXRATEMODE = pwr_on_fsm ? USER_TXRATEMODE : 1'b1;
        assign USER_GTPOWERGOOD = pwr_on_fsm;
        end
        endgenerate
        endmodule
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_top.v deleted 100644 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        `timescale 1ps/1ps
        // =====================================================================================================================
        // This example design top module instantiates the example design wrapper; slices vectored ports for per-channel
        // assignment; and instantiates example resources such as buffers, pattern generators, and pattern checkers for core
        // demonstration purposes
        // =====================================================================================================================
        module gtwizard_ultrascale_2_example_top (
        // Differential reference clock inputs
        input wire mgtrefclk0_x0y0_p,
        input wire mgtrefclk0_x0y0_n,
        // Serial data ports for transceiver channel 0
        input wire ch0_gthrxn_in,
        input wire ch0_gthrxp_in,
        output wire ch0_gthtxn_out,
        output wire ch0_gthtxp_out,
        // User-provided ports for reset helper block(s)
        input wire hb_gtwiz_reset_clk_freerun_in,
        input wire hb_gtwiz_reset_all_in,
        // PRBS-based link status ports
        input wire link_down_latched_reset_in,
        output wire link_status_out,
        output reg link_down_latched_out = 1'b1
        );
        // ===================================================================================================================
        // PER-CHANNEL SIGNAL ASSIGNMENTS
        // ===================================================================================================================
        // The core and example design wrapper vectorize ports across all enabled transceiver channel and common instances for
        // simplicity and compactness. This example design top module assigns slices of each vector to individual, per-channel
        // signal vectors for use if desired. Signals which connect to helper blocks are prefixed "hb#", signals which connect
        // to transceiver common primitives are prefixed "cm#", and signals which connect to transceiver channel primitives
        // are prefixed "ch#", where "#" is the sequential resource number.
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gthrxn_int;
        assign gthrxn_int[0:0] = ch0_gthrxn_in;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gthrxp_int;
        assign gthrxp_int[0:0] = ch0_gthrxp_in;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gthtxn_int;
        assign ch0_gthtxn_out = gthtxn_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gthtxp_int;
        assign ch0_gthtxp_out = gthtxp_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_tx_reset_int;
        wire [0:0] hb0_gtwiz_userclk_tx_reset_int;
        assign gtwiz_userclk_tx_reset_int[0:0] = hb0_gtwiz_userclk_tx_reset_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_tx_srcclk_int;
        wire [0:0] hb0_gtwiz_userclk_tx_srcclk_int;
        assign hb0_gtwiz_userclk_tx_srcclk_int = gtwiz_userclk_tx_srcclk_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_tx_usrclk_int;
        wire [0:0] hb0_gtwiz_userclk_tx_usrclk_int;
        assign hb0_gtwiz_userclk_tx_usrclk_int = gtwiz_userclk_tx_usrclk_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_tx_usrclk2_int;
        wire [0:0] hb0_gtwiz_userclk_tx_usrclk2_int;
        assign hb0_gtwiz_userclk_tx_usrclk2_int = gtwiz_userclk_tx_usrclk2_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_tx_active_int;
        wire [0:0] hb0_gtwiz_userclk_tx_active_int;
        assign hb0_gtwiz_userclk_tx_active_int = gtwiz_userclk_tx_active_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_rx_reset_int;
        wire [0:0] hb0_gtwiz_userclk_rx_reset_int;
        assign gtwiz_userclk_rx_reset_int[0:0] = hb0_gtwiz_userclk_rx_reset_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_rx_srcclk_int;
        wire [0:0] hb0_gtwiz_userclk_rx_srcclk_int;
        assign hb0_gtwiz_userclk_rx_srcclk_int = gtwiz_userclk_rx_srcclk_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_rx_usrclk_int;
        wire [0:0] hb0_gtwiz_userclk_rx_usrclk_int;
        assign hb0_gtwiz_userclk_rx_usrclk_int = gtwiz_userclk_rx_usrclk_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_rx_usrclk2_int;
        wire [0:0] hb0_gtwiz_userclk_rx_usrclk2_int;
        assign hb0_gtwiz_userclk_rx_usrclk2_int = gtwiz_userclk_rx_usrclk2_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_userclk_rx_active_int;
        wire [0:0] hb0_gtwiz_userclk_rx_active_int;
        assign hb0_gtwiz_userclk_rx_active_int = gtwiz_userclk_rx_active_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_tx_reset_int;
        wire [0:0] hb0_gtwiz_buffbypass_tx_reset_int;
        assign gtwiz_buffbypass_tx_reset_int[0:0] = hb0_gtwiz_buffbypass_tx_reset_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_tx_start_user_int;
        wire [0:0] hb0_gtwiz_buffbypass_tx_start_user_int = 1'b0;
        assign gtwiz_buffbypass_tx_start_user_int[0:0] = hb0_gtwiz_buffbypass_tx_start_user_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_tx_done_int;
        wire [0:0] hb0_gtwiz_buffbypass_tx_done_int;
        assign hb0_gtwiz_buffbypass_tx_done_int = gtwiz_buffbypass_tx_done_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_tx_error_int;
        wire [0:0] hb0_gtwiz_buffbypass_tx_error_int;
        assign hb0_gtwiz_buffbypass_tx_error_int = gtwiz_buffbypass_tx_error_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_rx_reset_int;
        wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int;
        assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_rx_start_user_int;
        wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0;
        assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_rx_done_int;
        wire [0:0] hb0_gtwiz_buffbypass_rx_done_int;
        assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_buffbypass_rx_error_int;
        wire [0:0] hb0_gtwiz_buffbypass_rx_error_int;
        assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_clk_freerun_int;
        wire [0:0] hb0_gtwiz_reset_clk_freerun_int = 1'b0;
        assign gtwiz_reset_clk_freerun_int[0:0] = hb0_gtwiz_reset_clk_freerun_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_all_int;
        wire [0:0] hb0_gtwiz_reset_all_int = 1'b0;
        assign gtwiz_reset_all_int[0:0] = hb0_gtwiz_reset_all_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_tx_pll_and_datapath_int;
        wire [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int;
        assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_tx_datapath_int;
        wire [0:0] hb0_gtwiz_reset_tx_datapath_int;
        assign gtwiz_reset_tx_datapath_int[0:0] = hb0_gtwiz_reset_tx_datapath_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_rx_pll_and_datapath_int;
        wire [0:0] hb0_gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
        assign gtwiz_reset_rx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_rx_pll_and_datapath_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_rx_datapath_int;
        wire [0:0] hb0_gtwiz_reset_rx_datapath_int = 1'b0;
        assign gtwiz_reset_rx_datapath_int[0:0] = hb0_gtwiz_reset_rx_datapath_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_rx_cdr_stable_int;
        wire [0:0] hb0_gtwiz_reset_rx_cdr_stable_int;
        assign hb0_gtwiz_reset_rx_cdr_stable_int = gtwiz_reset_rx_cdr_stable_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_tx_done_int;
        wire [0:0] hb0_gtwiz_reset_tx_done_int;
        assign hb0_gtwiz_reset_tx_done_int = gtwiz_reset_tx_done_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtwiz_reset_rx_done_int;
        wire [0:0] hb0_gtwiz_reset_rx_done_int;
        assign hb0_gtwiz_reset_rx_done_int = gtwiz_reset_rx_done_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] gtwiz_userdata_tx_int;
        wire [15:0] hb0_gtwiz_userdata_tx_int;
        assign gtwiz_userdata_tx_int[15:0] = hb0_gtwiz_userdata_tx_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] gtwiz_userdata_rx_int;
        wire [15:0] hb0_gtwiz_userdata_rx_int;
        assign hb0_gtwiz_userdata_rx_int = gtwiz_userdata_rx_int[15:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [9:0] drpaddr_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] drpclk_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] drpdi_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] drpen_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] drpwe_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] eyescanreset_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtrefclk0_int;
        wire [0:0] ch0_gtrefclk0_int;
        assign gtrefclk0_int[0:0] = ch0_gtrefclk0_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rx8b10ben_int;
        wire [0:0] ch0_rx8b10ben_int = 1'b1;
        assign rx8b10ben_int[0:0] = ch0_rx8b10ben_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxcommadeten_int;
        wire [0:0] ch0_rxcommadeten_int = 1'b1;
        assign rxcommadeten_int[0:0] = ch0_rxcommadeten_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxlpmen_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxmcommaalignen_int;
        wire [0:0] ch0_rxmcommaalignen_int = 1'b1;
        assign rxmcommaalignen_int[0:0] = ch0_rxmcommaalignen_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxpcommaalignen_int;
        wire [0:0] ch0_rxpcommaalignen_int = 1'b1;
        assign rxpcommaalignen_int[0:0] = ch0_rxpcommaalignen_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [2:0] rxrate_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxslide_int;
        wire [0:0] ch0_rxslide_int = 1'b0;
        assign rxslide_int[0:0] = ch0_rxslide_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] tx8b10ben_int;
        wire [0:0] ch0_tx8b10ben_int = 1'b1;
        assign tx8b10ben_int[0:0] = ch0_tx8b10ben_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] txctrl0_int;
        wire [15:0] ch0_txctrl0_int;
        assign txctrl0_int[15:0] = ch0_txctrl0_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] txctrl1_int;
        wire [15:0] ch0_txctrl1_int;
        assign txctrl1_int[15:0] = ch0_txctrl1_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [7:0] txctrl2_int;
        wire [7:0] ch0_txctrl2_int;
        assign txctrl2_int[7:0] = ch0_txctrl2_int;
        //--------------------------------------------------------------------------------------------------------------------
        wire [4:0] txdiffctrl_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [4:0] txpostcursor_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [4:0] txprecursor_int;
        // This vector is not sliced because it is directly assigned in a debug core instance below
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] drpdo_int;
        wire [15:0] ch0_drpdo_int;
        assign ch0_drpdo_int = drpdo_int[15:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] drprdy_int;
        wire [0:0] ch0_drprdy_int;
        assign ch0_drprdy_int = drprdy_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] gtpowergood_int;
        wire [0:0] ch0_gtpowergood_int;
        assign ch0_gtpowergood_int = gtpowergood_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxbyteisaligned_int;
        wire [0:0] ch0_rxbyteisaligned_int;
        assign ch0_rxbyteisaligned_int = rxbyteisaligned_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxbyterealign_int;
        wire [0:0] ch0_rxbyterealign_int;
        assign ch0_rxbyterealign_int = rxbyterealign_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxcommadet_int;
        wire [0:0] ch0_rxcommadet_int;
        assign ch0_rxcommadet_int = rxcommadet_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] rxctrl0_int;
        wire [15:0] ch0_rxctrl0_int;
        assign ch0_rxctrl0_int = rxctrl0_int[15:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [15:0] rxctrl1_int;
        wire [15:0] ch0_rxctrl1_int;
        assign ch0_rxctrl1_int = rxctrl1_int[15:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [7:0] rxctrl2_int;
        wire [7:0] ch0_rxctrl2_int;
        assign ch0_rxctrl2_int = rxctrl2_int[7:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [7:0] rxctrl3_int;
        wire [7:0] ch0_rxctrl3_int;
        assign ch0_rxctrl3_int = rxctrl3_int[7:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] rxpmaresetdone_int;
        wire [0:0] ch0_rxpmaresetdone_int;
        assign ch0_rxpmaresetdone_int = rxpmaresetdone_int[0:0];
        //--------------------------------------------------------------------------------------------------------------------
        wire [0:0] txpmaresetdone_int;
        wire [0:0] ch0_txpmaresetdone_int;
        assign ch0_txpmaresetdone_int = txpmaresetdone_int[0:0];
        // ===================================================================================================================
        // BUFFERS
        // ===================================================================================================================
        // Buffer the hb_gtwiz_reset_all_in input and logically combine it with the internal signal from the example
        // initialization block as well as the VIO-sourced reset
        wire hb_gtwiz_reset_all_vio_int;
        wire hb_gtwiz_reset_all_buf_int;
        wire hb_gtwiz_reset_all_init_int;
        wire hb_gtwiz_reset_all_int;
        IBUF ibuf_hb_gtwiz_reset_all_inst (
        .I (hb_gtwiz_reset_all_in),
        .O (hb_gtwiz_reset_all_buf_int)
        );
        assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int || hb_gtwiz_reset_all_vio_int;
        // Globally buffer the free-running input clock
        wire hb_gtwiz_reset_clk_freerun_buf_int;
        BUFG bufg_clk_freerun_inst (
        .I (hb_gtwiz_reset_clk_freerun_in),
        .O (hb_gtwiz_reset_clk_freerun_buf_int)
        );
        // Instantiate a differential reference clock buffer for each reference clock differential pair in this configuration,
        // and assign the single-ended output of each differential reference clock buffer to the appropriate PLL input signal
        // Differential reference clock buffer for MGTREFCLK0_X0Y0
        wire mgtrefclk0_x0y0_int;
        IBUFDS_GTE4 #(
        .REFCLK_EN_TX_PATH (1'b0),
        .REFCLK_HROW_CK_SEL (2'b00),
        .REFCLK_ICNTL_RX (2'b00)
        ) IBUFDS_GTE4_MGTREFCLK0_X0Y0_INST (
        .I (mgtrefclk0_x0y0_p),
        .IB (mgtrefclk0_x0y0_n),
        .CEB (1'b0),
        .O (mgtrefclk0_x0y0_int),
        .ODIV2 ()
        );
        assign ch0_gtrefclk0_int = mgtrefclk0_x0y0_int;
        // ===================================================================================================================
        // USER CLOCKING RESETS
        // ===================================================================================================================
        // The TX user clocking helper block should be held in reset until the clock source of that block is known to be
        // stable. The following assignment is an example of how that stability can be determined, based on the selected TX
        // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed.
        assign hb0_gtwiz_userclk_tx_reset_int = ~(&txpmaresetdone_int);
        // The RX user clocking helper block should be held in reset until the clock source of that block is known to be
        // stable. The following assignment is an example of how that stability can be determined, based on the selected RX
        // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed.
        assign hb0_gtwiz_userclk_rx_reset_int = ~(&rxpmaresetdone_int);
        // ===================================================================================================================
        // BUFFER BYPASS CONTROLLER RESETS
        // ===================================================================================================================
        // The TX buffer bypass controller helper block should be held in reset until the TX user clocking network helper
        // block which drives it is active
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_tx_reset_inst (
        .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int),
        .rst_in (~hb0_gtwiz_userclk_tx_active_int),
        .rst_out (hb0_gtwiz_buffbypass_tx_reset_int)
        );
        // The RX buffer bypass controller helper block should be held in reset until the RX user clocking network helper
        // block which drives it is active and the TX buffer bypass sequence has completed for this loopback configuration
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_rx_reset_inst (
        .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int),
        .rst_in (~hb0_gtwiz_userclk_rx_active_int || ~hb0_gtwiz_buffbypass_tx_done_int),
        .rst_out (hb0_gtwiz_buffbypass_rx_reset_int)
        );
        // ===================================================================================================================
        // PRBS STIMULUS, CHECKING, AND LINK MANAGEMENT
        // ===================================================================================================================
        // PRBS stimulus
        // -------------------------------------------------------------------------------------------------------------------
        // PRBS-based data stimulus module for transceiver channel 0
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_stimulus_8b10b example_stimulus_inst0 (
        .gtwiz_reset_all_in (hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int || ~hb0_gtwiz_buffbypass_tx_done_int),
        .gtwiz_userclk_tx_usrclk2_in (hb0_gtwiz_userclk_tx_usrclk2_int),
        .gtwiz_userclk_tx_active_in (hb0_gtwiz_userclk_tx_active_int),
        .txctrl0_out (ch0_txctrl0_int),
        .txctrl1_out (ch0_txctrl1_int),
        .txctrl2_out (ch0_txctrl2_int),
        .txdata_out (hb0_gtwiz_userdata_tx_int)
        );
        // PRBS checking
        // -------------------------------------------------------------------------------------------------------------------
        // Declare a signal vector of PRBS match indicators, with one indicator bit per transceiver channel
        wire [0:0] prbs_match_int;
        // PRBS-based data checking module for transceiver channel 0
        gtwizard_ultrascale_2_example_checking_8b10b example_checking_inst0 (
        .gtwiz_reset_all_in (hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int || ~hb0_gtwiz_buffbypass_tx_done_int),
        .gtwiz_userclk_rx_usrclk2_in (hb0_gtwiz_userclk_rx_usrclk2_int),
        .gtwiz_userclk_rx_active_in (hb0_gtwiz_userclk_rx_active_int),
        .rxctrl0_in (ch0_rxctrl0_int),
        .rxctrl1_in (ch0_rxctrl1_int),
        .rxctrl2_in (ch0_rxctrl2_int),
        .rxctrl3_in (ch0_rxctrl3_int),
        .rxdata_in (hb0_gtwiz_userdata_rx_int),
        .prbs_match_out (prbs_match_int[0])
        );
        // PRBS match and related link management
        // -------------------------------------------------------------------------------------------------------------------
        // Perform a bitwise NAND of all PRBS match indicators, creating a combinatorial indication of any PRBS mismatch
        // across all transceiver channels
        wire prbs_error_any_async = ~(&prbs_match_int);
        wire prbs_error_any_sync;
        // Synchronize the PRBS mismatch indicator the free-running clock domain, using a reset synchronizer with asynchronous
        // reset and synchronous removal
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_reset_synchronizer reset_synchronizer_prbs_match_all_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .rst_in (prbs_error_any_async),
        .rst_out(prbs_error_any_sync)
        );
        // Implement an example link status state machine using a simple leaky bucket mechanism. The link status indicates
        // the continual PRBS match status to both the top-level observer and the initialization state machine, while being
        // tolerant of occasional bit errors. This is an example and can be modified as necessary.
        localparam ST_LINK_DOWN = 1'b0;
        localparam ST_LINK_UP = 1'b1;
        reg sm_link = ST_LINK_DOWN;
        reg [6:0] link_ctr = 7'd0;
        always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin
        case (sm_link)
        // The link is considered to be down when the link counter initially has a value less than 67. When the link is
        // down, the counter is incremented on each cycle where all PRBS bits match, but reset whenever any PRBS mismatch
        // occurs. When the link counter reaches 67, transition to the link up state.
        ST_LINK_DOWN: begin
        if (prbs_error_any_sync !== 1'b0) begin
        link_ctr <= 7'd0;
        end
        else begin
        if (link_ctr < 7'd67)
        link_ctr <= link_ctr + 7'd1;
        else
        sm_link <= ST_LINK_UP;
        end
        end
        // When the link is up, the link counter is decreased by 34 whenever any PRBS mismatch occurs, but is increased by
        // only 1 on each cycle where all PRBS bits match, up to its saturation point of 67. If the link counter reaches
        // 0 (including rollover protection), transition to the link down state.
        ST_LINK_UP: begin
        if (prbs_error_any_sync !== 1'b0) begin
        if (link_ctr > 7'd33) begin
        link_ctr <= link_ctr - 7'd34;
        if (link_ctr == 7'd34)
        sm_link <= ST_LINK_DOWN;
        end
        else begin
        link_ctr <= 7'd0;
        sm_link <= ST_LINK_DOWN;
        end
        end
        else begin
        if (link_ctr < 7'd67)
        link_ctr <= link_ctr + 7'd1;
        end
        end
        endcase
        end
        // Synchronize the latched link down reset input and the VIO-driven signal into the free-running clock domain
        wire link_down_latched_reset_vio_int;
        wire link_down_latched_reset_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_link_down_latched_reset_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (link_down_latched_reset_in || link_down_latched_reset_vio_int),
        .o_out (link_down_latched_reset_sync)
        );
        // Reset the latched link down indicator when the synchronized latched link down reset signal is high. Otherwise, set
        // the latched link down indicator upon losing link. This indicator is available for user reference.
        always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin
        if (link_down_latched_reset_sync)
        link_down_latched_out <= 1'b0;
        else if (!sm_link)
        link_down_latched_out <= 1'b1;
        end
        // Assign the link status indicator to the top-level two-state output for user reference
        assign link_status_out = sm_link;
        // ===================================================================================================================
        // INITIALIZATION
        // ===================================================================================================================
        // Declare the receiver reset signals that interface to the reset controller helper block. For this configuration,
        // which uses the same PLL type for transmitter and receiver, the "reset RX PLL and datapath" feature is not used.
        wire hb_gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
        wire hb_gtwiz_reset_rx_datapath_int;
        // Declare signals which connect the VIO instance to the initialization module for debug purposes
        wire init_done_int;
        wire [3:0] init_retry_ctr_int;
        // Combine the receiver reset signals form the initialization module and the VIO to drive the appropriate reset
        // controller helper block reset input
        wire hb_gtwiz_reset_rx_pll_and_datapath_vio_int;
        wire hb_gtwiz_reset_rx_datapath_vio_int;
        wire hb_gtwiz_reset_rx_datapath_init_int;
        assign hb_gtwiz_reset_rx_datapath_int = hb_gtwiz_reset_rx_datapath_init_int || hb_gtwiz_reset_rx_datapath_vio_int;
        // The example initialization module interacts with the reset controller helper block and other example design logic
        // to retry failed reset attempts in order to mitigate bring-up issues such as initially-unavilable reference clocks
        // or data connections. It also resets the receiver in the event of link loss in an attempt to regain link, so please
        // note the possibility that this behavior can have the effect of overriding or disturbing user-provided inputs that
        // destabilize the data stream. It is a demonstration only and can be modified to suit your system needs.
        gtwizard_ultrascale_2_example_init example_init_inst (
        .clk_freerun_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .reset_all_in (hb_gtwiz_reset_all_int),
        .tx_init_done_in (gtwiz_reset_tx_done_int && gtwiz_buffbypass_tx_done_int),
        .rx_init_done_in (gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int),
        .rx_data_good_in (sm_link),
        .reset_all_out (hb_gtwiz_reset_all_init_int),
        .reset_rx_out (hb_gtwiz_reset_rx_datapath_init_int),
        .init_done_out (init_done_int),
        .retry_ctr_out (init_retry_ctr_int)
        );
        // ===================================================================================================================
        // VIO FOR HARDWARE BRING-UP AND DEBUG
        // ===================================================================================================================
        // Synchronize gtpowergood into the free-running clock domain for VIO usage
        wire [0:0] gtpowergood_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtpowergood_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtpowergood_int[0]),
        .o_out (gtpowergood_vio_sync[0])
        );
        // Synchronize txpmaresetdone into the free-running clock domain for VIO usage
        wire [0:0] txpmaresetdone_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_txpmaresetdone_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (txpmaresetdone_int[0]),
        .o_out (txpmaresetdone_vio_sync[0])
        );
        // Synchronize rxpmaresetdone into the free-running clock domain for VIO usage
        wire [0:0] rxpmaresetdone_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_rxpmaresetdone_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (rxpmaresetdone_int[0]),
        .o_out (rxpmaresetdone_vio_sync[0])
        );
        // Synchronize gtwiz_reset_tx_done into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_reset_tx_done_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_tx_done_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_reset_tx_done_int[0]),
        .o_out (gtwiz_reset_tx_done_vio_sync[0])
        );
        // Synchronize gtwiz_reset_rx_done into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_reset_rx_done_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_rx_done_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_reset_rx_done_int[0]),
        .o_out (gtwiz_reset_rx_done_vio_sync[0])
        );
        // Synchronize gtwiz_buffbypass_tx_done into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_buffbypass_tx_done_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_tx_done_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_buffbypass_tx_done_int[0]),
        .o_out (gtwiz_buffbypass_tx_done_vio_sync[0])
        );
        // Synchronize gtwiz_buffbypass_rx_done into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_buffbypass_rx_done_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_done_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_buffbypass_rx_done_int[0]),
        .o_out (gtwiz_buffbypass_rx_done_vio_sync[0])
        );
        // Synchronize gtwiz_buffbypass_tx_error into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_buffbypass_tx_error_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_tx_error_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_buffbypass_tx_error_int[0]),
        .o_out (gtwiz_buffbypass_tx_error_vio_sync[0])
        );
        // Synchronize gtwiz_buffbypass_rx_error into the free-running clock domain for VIO usage
        wire [0:0] gtwiz_buffbypass_rx_error_vio_sync;
        (* DONT_TOUCH = "TRUE" *)
        gtwizard_ultrascale_2_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_error_0_inst (
        .clk_in (hb_gtwiz_reset_clk_freerun_buf_int),
        .i_in (gtwiz_buffbypass_rx_error_int[0]),
        .o_out (gtwiz_buffbypass_rx_error_vio_sync[0])
        );
        // Instantiate the VIO IP core for hardware bring-up and debug purposes, connecting relevant debug and analysis
        // signals which have been enabled during Wizard IP customization. This initial set of connected signals is
        // provided as a convenience and example, but more or fewer ports can be used as needed; simply re-customize and
        // re-generate the VIO instance, then connect any exposed signals that are needed. Signals which are synchronous to
        // clocks other than the free-running clock will require synchronization. For usage, refer to Vivado Design Suite
        // User Guide: Programming and Debugging (UG908)
        gtwizard_ultrascale_2_vio_0 gtwizard_ultrascale_2_vio_0_inst (
        .clk (hb_gtwiz_reset_clk_freerun_buf_int)
        ,.probe_in0 (link_status_out)
        ,.probe_in1 (link_down_latched_out)
        ,.probe_in2 (init_done_int)
        ,.probe_in3 (init_retry_ctr_int)
        ,.probe_in4 (gtpowergood_vio_sync)
        ,.probe_in5 (txpmaresetdone_vio_sync)
        ,.probe_in6 (rxpmaresetdone_vio_sync)
        ,.probe_in7 (gtwiz_reset_tx_done_vio_sync)
        ,.probe_in8 (gtwiz_reset_rx_done_vio_sync)
        ,.probe_in9 (gtwiz_buffbypass_tx_done_vio_sync)
        ,.probe_in10 (gtwiz_buffbypass_rx_done_vio_sync)
        ,.probe_in11 (gtwiz_buffbypass_tx_error_vio_sync)
        ,.probe_in12 (gtwiz_buffbypass_rx_error_vio_sync)
        ,.probe_out0 (hb_gtwiz_reset_all_vio_int)
        ,.probe_out1 (hb0_gtwiz_reset_tx_pll_and_datapath_int)
        ,.probe_out2 (hb0_gtwiz_reset_tx_datapath_int)
        ,.probe_out3 (hb_gtwiz_reset_rx_pll_and_datapath_vio_int)
        ,.probe_out4 (hb_gtwiz_reset_rx_datapath_vio_int)
        ,.probe_out5 (link_down_latched_reset_vio_int)
        );
        // ===================================================================================================================
        // IN-SYSTEM IBERT FOR HARDWARE BRING-UP AND LINK ANALYSIS
        // ===================================================================================================================
        // Instantiate the In-System IBERT IP core for hardware bring-up and link analysis purposes. For usage, refer to
        // Vivado Design Suite User Guide: Programming and Debugging (UG908)
        // In-System IBERT IP instance property dictionary is as follows:
        // CONFIG.C_GT_TYPE {GTH} CONFIG.C_GTS_USED {X0Y0} CONFIG.C_ENABLE_INPUT_PORTS {true}
        gtwizard_ultrascale_2_in_system_ibert_0 gtwizard_ultrascale_2_in_system_ibert_0_inst (
        .drpclk_o (drpclk_int),
        .gt0_drpen_o (drpen_int[0:0]),
        .gt0_drpwe_o (drpwe_int[0:0]),
        .gt0_drpaddr_o (drpaddr_int[9:0]),
        .gt0_drpdi_o (drpdi_int[15:0]),
        .gt0_drprdy_i (drprdy_int[0:0]),
        .gt0_drpdo_i (drpdo_int[15:0]),
        .eyescanreset_o (eyescanreset_int),
        .rxrate_o (rxrate_int),
        .txdiffctrl_o (txdiffctrl_int),
        .txprecursor_o (txprecursor_int),
        .txpostcursor_o (txpostcursor_int),
        .rxlpmen_o (rxlpmen_int),
        .rxrate_i ({1{3'b000}}),
        .txdiffctrl_i ({1{5'b11000}}),
        .txprecursor_i ({1{5'b00000}}),
        .txpostcursor_i ({1{5'b00000}}),
        .rxlpmen_i ({1{1'b1}}),
        .rxoutclk_i ({1{hb0_gtwiz_userclk_rx_usrclk2_int}}),
        .drpclk_i ({1{hb_gtwiz_reset_clk_freerun_buf_int}}),
        .clk (hb_gtwiz_reset_clk_freerun_buf_int)
        );
        // ===================================================================================================================
        // EXAMPLE WRAPPER INSTANCE
        // ===================================================================================================================
        // Instantiate the example design wrapper, mapping its enabled ports to per-channel internal signals and example
        // resources as appropriate
        gtwizard_ultrascale_2_example_wrapper example_wrapper_inst (
        .gthrxn_in (gthrxn_int)
        ,.gthrxp_in (gthrxp_int)
        ,.gthtxn_out (gthtxn_int)
        ,.gthtxp_out (gthtxp_int)
        ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int)
        ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_int)
        ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_int)
        ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_int)
        ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)
        ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int)
        ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_int)
        ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_int)
        ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_int)
        ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_int)
        ,.gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_int)
        ,.gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_int)
        ,.gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_int)
        ,.gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_int)
        ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_int)
        ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_int)
        ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_int)
        ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_int)
        ,.gtwiz_reset_clk_freerun_in ({1{hb_gtwiz_reset_clk_freerun_buf_int}})
        ,.gtwiz_reset_all_in ({1{hb_gtwiz_reset_all_int}})
        ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_int)
        ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_int)
        ,.gtwiz_reset_rx_pll_and_datapath_in ({1{hb_gtwiz_reset_rx_pll_and_datapath_int}})
        ,.gtwiz_reset_rx_datapath_in ({1{hb_gtwiz_reset_rx_datapath_int}})
        ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_int)
        ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_int)
        ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_int)
        ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_int)
        ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_int)
        ,.drpaddr_in (drpaddr_int)
        ,.drpclk_in (drpclk_int)
        ,.drpdi_in (drpdi_int)
        ,.drpen_in (drpen_int)
        ,.drpwe_in (drpwe_int)
        ,.eyescanreset_in (eyescanreset_int)
        ,.gtrefclk0_in (gtrefclk0_int)
        ,.rx8b10ben_in (rx8b10ben_int)
        ,.rxcommadeten_in (rxcommadeten_int)
        ,.rxlpmen_in (rxlpmen_int)
        ,.rxmcommaalignen_in (rxmcommaalignen_int)
        ,.rxpcommaalignen_in (rxpcommaalignen_int)
        ,.rxrate_in (rxrate_int)
        ,.rxslide_in (rxslide_int)
        ,.tx8b10ben_in (tx8b10ben_int)
        ,.txctrl0_in (txctrl0_int)
        ,.txctrl1_in (txctrl1_int)
        ,.txctrl2_in (txctrl2_int)
        ,.txdiffctrl_in (txdiffctrl_int)
        ,.txpostcursor_in (txpostcursor_int)
        ,.txprecursor_in (txprecursor_int)
        ,.drpdo_out (drpdo_int)
        ,.drprdy_out (drprdy_int)
        ,.gtpowergood_out (gtpowergood_int)
        ,.rxbyteisaligned_out (rxbyteisaligned_int)
        ,.rxbyterealign_out (rxbyterealign_int)
        ,.rxcommadet_out (rxcommadet_int)
        ,.rxctrl0_out (rxctrl0_int)
        ,.rxctrl1_out (rxctrl1_int)
        ,.rxctrl2_out (rxctrl2_int)
        ,.rxctrl3_out (rxctrl3_int)
        ,.rxpmaresetdone_out (rxpmaresetdone_int)
        ,.txpmaresetdone_out (txpmaresetdone_int)
        );
        endmodule
        platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_wrapper.v deleted 100644 → 0
        View file @ 0fbb5a20
        //------------------------------------------------------------------------------
        // (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
        //
        // This file contains confidential and proprietary information
        // of Xilinx, Inc. and is protected under U.S. and
        // international copyright and other intellectual property
        // laws.
        //
        // DISCLAIMER
        // This disclaimer is not a license and does not grant any
        // rights to the materials distributed herewith. Except as
        // otherwise provided in a valid license issued to you by
        // Xilinx, and to the maximum extent permitted by applicable
        // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
        // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
        // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
        // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
        // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
        // (2) Xilinx shall not be liable (whether in contract or tort,
        // including negligence, or under any other theory of
        // liability) for any loss or damage of any kind or nature
        // related to, arising under or in connection with these
        // materials, including for any direct, or any indirect,
        // special, incidental, or consequential loss or damage
        // (including loss of data, profits, goodwill, or any type of
        // loss or damage suffered as a result of any action brought
        // by a third party) even if such damage or loss was
        // reasonably foreseeable or Xilinx had been advised of the
        // possibility of the same.
        //
        // CRITICAL APPLICATIONS
        // Xilinx products are not designed or intended to be fail-
        // safe, or for use in any application requiring fail-safe
        // performance, such as life-support or safety devices or
        // systems, Class III medical devices, nuclear facilities,
        // applications related to the deployment of airbags, or any
        // other applications that could lead to death, personal
        // injury, or severe property or environmental damage
        // (individually and collectively, "Critical
        // Applications"). Customer assumes the sole risk and
        // liability of any use of Xilinx products in Critical
        // Applications, subject only to applicable laws and
        // regulations governing limitations on product liability.
        //
        // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
        // PART OF THIS FILE AT ALL TIMES.
        //------------------------------------------------------------------------------
        `timescale 1ps/1ps
        // =====================================================================================================================
        // This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from
        // the core, connects them as appropriate, and maps enabled ports
        // =====================================================================================================================
        module gtwizard_ultrascale_2_example_wrapper (
        input wire [0:0] gthrxn_in
        ,input wire [0:0] gthrxp_in
        ,output wire [0:0] gthtxn_out
        ,output wire [0:0] gthtxp_out
        ,input wire [0:0] gtwiz_userclk_tx_reset_in
        ,output wire [0:0] gtwiz_userclk_tx_srcclk_out
        ,output wire [0:0] gtwiz_userclk_tx_usrclk_out
        ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out
        ,output wire [0:0] gtwiz_userclk_tx_active_out
        ,input wire [0:0] gtwiz_userclk_rx_reset_in
        ,output wire [0:0] gtwiz_userclk_rx_srcclk_out
        ,output wire [0:0] gtwiz_userclk_rx_usrclk_out
        ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out
        ,output wire [0:0] gtwiz_userclk_rx_active_out
        ,input wire [0:0] gtwiz_buffbypass_tx_reset_in
        ,input wire [0:0] gtwiz_buffbypass_tx_start_user_in
        ,output wire [0:0] gtwiz_buffbypass_tx_done_out
        ,output wire [0:0] gtwiz_buffbypass_tx_error_out
        ,input wire [0:0] gtwiz_buffbypass_rx_reset_in
        ,input wire [0:0] gtwiz_buffbypass_rx_start_user_in
        ,output wire [0:0] gtwiz_buffbypass_rx_done_out
        ,output wire [0:0] gtwiz_buffbypass_rx_error_out
        ,input wire [0:0] gtwiz_reset_clk_freerun_in
        ,input wire [0:0] gtwiz_reset_all_in
        ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in
        ,input wire [0:0] gtwiz_reset_tx_datapath_in
        ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in
        ,input wire [0:0] gtwiz_reset_rx_datapath_in
        ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out
        ,output wire [0:0] gtwiz_reset_tx_done_out
        ,output wire [0:0] gtwiz_reset_rx_done_out
        ,input wire [15:0] gtwiz_userdata_tx_in
        ,output wire [15:0] gtwiz_userdata_rx_out
        ,input wire [9:0] drpaddr_in
        ,input wire [0:0] drpclk_in
        ,input wire [15:0] drpdi_in
        ,input wire [0:0] drpen_in
        ,input wire [0:0] drpwe_in
        ,input wire [0:0] eyescanreset_in
        ,input wire [0:0] gtrefclk0_in
        ,input wire [0:0] rx8b10ben_in
        ,input wire [0:0] rxcommadeten_in
        ,input wire [0:0] rxlpmen_in
        ,input wire [0:0] rxmcommaalignen_in
        ,input wire [0:0] rxpcommaalignen_in
        ,input wire [2:0] rxrate_in
        ,input wire [0:0] rxslide_in
        ,input wire [0:0] tx8b10ben_in
        ,input wire [15:0] txctrl0_in
        ,input wire [15:0] txctrl1_in
        ,input wire [7:0] txctrl2_in
        ,input wire [4:0] txdiffctrl_in
        ,input wire [4:0] txpostcursor_in
        ,input wire [4:0] txprecursor_in
        ,output wire [15:0] drpdo_out
        ,output wire [0:0] drprdy_out
        ,output wire [0:0] gtpowergood_out
        ,output wire [0:0] rxbyteisaligned_out
        ,output wire [0:0] rxbyterealign_out
        ,output wire [0:0] rxcommadet_out
        ,output wire [15:0] rxctrl0_out
        ,output wire [15:0] rxctrl1_out
        ,output wire [7:0] rxctrl2_out
        ,output wire [7:0] rxctrl3_out
        ,output wire [0:0] rxpmaresetdone_out
        ,output wire [0:0] txpmaresetdone_out
        );
        // ===================================================================================================================
        // PARAMETERS AND FUNCTIONS
        // ===================================================================================================================
        // Declare and initialize local parameters and functions used for HDL generation
        localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
        `include "gtwizard_ultrascale_2_example_wrapper_functions.v"
        localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(0);
        localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(0);
        // ===================================================================================================================
        // HELPER BLOCKS
        // ===================================================================================================================
        // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal
        // assignments related to optionally-enabled ports may appear below.
        wire [0:0] gtpowergood_int;
        // Required assignment to expose the GTPOWERGOOD port per user request
        assign gtpowergood_out = gtpowergood_int;
        // ----------------------------------------------------------------------------------------------------------------
        // Assignments to expose data ports, or data control ports, per configuration requirement or user request
        // ----------------------------------------------------------------------------------------------------------------
        wire [15:0] txctrl0_int;
        // Required assignment to expose the TXCTRL0 port per configuration requirement or user request
        assign txctrl0_int = txctrl0_in;
        wire [15:0] txctrl1_int;
        // Required assignment to expose the TXCTRL1 port per configuration requirement or user request
        assign txctrl1_int = txctrl1_in;
        wire [15:0] rxctrl0_int;
        // Required assignment to expose the RXCTRL0 port per configuration requirement or user request
        assign rxctrl0_out = rxctrl0_int;
        wire [15:0] rxctrl1_int;
        // Required assignment to expose the RXCTRL1 port per configuration requirement or user request
        assign rxctrl1_out = rxctrl1_int;
        // ===================================================================================================================
        // CORE INSTANCE
        // ===================================================================================================================
        // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate
        gtwizard_ultrascale_2 gtwizard_ultrascale_2_inst (
        .gthrxn_in (gthrxn_in)
        ,.gthrxp_in (gthrxp_in)
        ,.gthtxn_out (gthtxn_out)
        ,.gthtxp_out (gthtxp_out)
        ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in)
        ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out)
        ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out)
        ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out)
        ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out)
        ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in)
        ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out)
        ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out)
        ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out)
        ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out)
        ,.gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in)
        ,.gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in)
        ,.gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out)
        ,.gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out)
        ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in)
        ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in)
        ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out)
        ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out)
        ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in)
        ,.gtwiz_reset_all_in (gtwiz_reset_all_in)
        ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in)
        ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in)
        ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in)
        ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in)
        ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out)
        ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out)
        ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out)
        ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in)
        ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out)
        ,.drpaddr_in (drpaddr_in)
        ,.drpclk_in (drpclk_in)
        ,.drpdi_in (drpdi_in)
        ,.drpen_in (drpen_in)
        ,.drpwe_in (drpwe_in)
        ,.eyescanreset_in (eyescanreset_in)
        ,.gtrefclk0_in (gtrefclk0_in)
        ,.rx8b10ben_in (rx8b10ben_in)
        ,.rxcommadeten_in (rxcommadeten_in)
        ,.rxlpmen_in (rxlpmen_in)
        ,.rxmcommaalignen_in (rxmcommaalignen_in)
        ,.rxpcommaalignen_in (rxpcommaalignen_in)
        ,.rxrate_in (rxrate_in)
        ,.rxslide_in (rxslide_in)
        ,.tx8b10ben_in (tx8b10ben_in)
        ,.txctrl0_in (txctrl0_int)
        ,.txctrl1_in (txctrl1_int)
        ,.txctrl2_in (txctrl2_in)
        ,.txdiffctrl_in (txdiffctrl_in)
        ,.txpostcursor_in (txpostcursor_in)
        ,.txprecursor_in (txprecursor_in)
        ,.drpdo_out (drpdo_out)
        ,.drprdy_out (drprdy_out)
        ,.gtpowergood_out (gtpowergood_int)
        ,.rxbyteisaligned_out (rxbyteisaligned_out)
        ,.rxbyterealign_out (rxbyterealign_out)
        ,.rxcommadet_out (rxcommadet_out)
        ,.rxctrl0_out (rxctrl0_int)
        ,.rxctrl1_out (rxctrl1_int)
        ,.rxctrl2_out (rxctrl2_out)
        ,.rxctrl3_out (rxctrl3_out)
        ,.rxpmaresetdone_out (rxpmaresetdone_out)
        ,.txpmaresetdone_out (txpmaresetdone_out)
        );
        endmodule
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