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Wishbone slave generator
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Wishbone slave generator
Commits
69883c7c
Commit
69883c7c
authored
Apr 18, 2018
by
Tomasz Wlostowski
1
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Merge remote-tracking branch 'origin/dlamprid-fix_unsupported_woro'
parents
6ee9c2e0
f27c2925
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Showing
2 changed files
with
42 additions
and
112 deletions
+42
-112
cgen_vhdl.lua
cgen_vhdl.lua
+38
-112
wbgen_regbank.lua
wbgen_regbank.lua
+4
-0
No files found.
cgen_vhdl.lua
View file @
69883c7c
...
...
@@ -18,14 +18,6 @@ fieldtype_2_vhdl[ENUM] = "std_logic_vector";
fieldtype_2_vhdl
[
SLV
]
=
"std_logic_vector"
;
function
get_pkg_name
()
if
(
periph
.
hdl_package
)
then
return
periph
.
hdl_package
else
return
periph
.
hdl_prefix
..
"_wbgen2_pkg"
;
end
end
-- generates a string containing VHDL-compatible numeric constant of value [value] and size [numbits]
function
gen_vhdl_bin_literal
(
value
,
numbits
)
if
(
numbits
==
1
)
then
...
...
@@ -58,16 +50,9 @@ function strip_periph_prefix(s)
return
string.gsub
(
s
,
"^"
..
periph
.
hdl_prefix
..
"\_"
,
""
)
end
function
strip_wb_prefix
(
s
)
local
t
=
string.gsub
(
s
,
"^wb\_"
,
""
)
t
=
string.gsub
(
t
,
"_o$"
,
""
)
t
=
string.gsub
(
t
,
"_i$"
,
""
)
return
t
end
-- fixme: do this neatly
function
port2record
(
s
)
if
(
options
.
hdl_reg_style
==
"signals
"
)
then
if
(
options
.
hdl_reg_style
~=
"record
"
)
then
return
s
end
...
...
@@ -75,23 +60,14 @@ function port2record(s)
if
(
port
.
name
==
s
and
port
.
is_reg_port
)
then
return
csel
(
port
.
dir
==
"in"
,
"regs_i."
,
"regs_o."
)
..
strip_periph_prefix
(
s
)
end
if
(
port
.
name
==
s
and
port
.
is_wb
and
options
.
hdl_reg_style
==
"record_full"
)
then
if
s
==
"wb_int_o"
then
return
"int_o"
;
end
return
csel
(
port
.
dir
==
"in"
,
"slave_i."
,
"slave_o."
)
..
strip_wb_prefix
(
s
)
end
end
return
s
end
function
cgen_vhdl_package
()
emit
(
"package "
..
get_pkg_name
()
..
" is"
)
local
pkg_name
=
periph
.
hdl_prefix
..
"_wbgen2_pkg"
;
emit
(
"package "
..
pkg_name
..
" is"
)
indent_right
();
emit
(
""
);
...
...
@@ -108,68 +84,50 @@ function cgen_vhdl_package()
cgen_vhdl_port_struct
(
"out"
);
indent_left
();
local
typename
=
"t_"
..
periph
.
hdl_prefix
..
"_in_registers"
;
emit
(
""
);
emit
(
"function \"
or
\
" (left, right: "
..
typename
..
") return "
..
typename
..
";"
);
emit
(
"function f_x_to_zero (x:std_logic) return std_logic;"
);
emit
(
"function f_x_to_zero (x:std_logic_vector) return std_logic_vector;"
);
emit
(
""
);
cgen_vhdl_interface_declaration
(
"component"
)
indent_left
();
indent_left
();
emit
(
"end package;"
);
emit
(
""
);
emit
(
"package body "
..
get_pkg_name
()
..
" is"
);
indent_right
();
emit
(
"package body "
..
pkg_name
..
" is"
);
emit
(
"function f_x_to_zero (x:std_logic) return std_logic is"
);
emit
(
"begin"
)
indent_right
();
emit
(
"if x = '1' then"
)
indent_right
();
emit
(
"return '1';"
)
indent_left
();
emit
(
"else"
)
indent_right
();
emit
(
"return '0';"
)
indent_left
();
emit
(
"end if;"
)
indent_left
();
emit
(
"end function;"
);
emit
(
""
)
emit
(
"function f_x_to_zero (x:std_logic_vector) return std_logic_vector is"
);
indent_right
();
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
indent_left
();
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
emit
(
"begin"
);
indent_right
();
emit
(
"for i in 0 to x'length-1 loop"
);
indent_right
();
emit
(
"if(x(i) = 'X' or x(i) = 'U') then"
);
indent_right
();
emit
(
"tmp(i):= '0';"
);
indent_left
();
emit
(
"if(x(i) = '1') then"
);
emit
(
"tmp(i):= '1';"
);
emit
(
"else"
);
indent_right
();
emit
(
"tmp(i):=x(i);"
);
indent_left
();
emit
(
"tmp(i):= '0';"
);
emit
(
"end if; "
);
indent_left
();
emit
(
"end loop; "
);
emit
(
"return tmp;"
);
indent_left
();
emit
(
"end function;"
);
emit
(
""
);
emit
(
"function \"
or
\
" (left, right: "
..
typename
..
") return "
..
typename
..
" is"
);
indent_right
();
emit
(
"variable tmp: "
..
typename
..
";"
);
indent_left
();
emit
(
"begin"
);
indent_right
();
for
i
=
1
,
table
.
getn
(
g_portlist
)
do
local
port
=
g_portlist
[
i
];
...
...
@@ -179,10 +137,8 @@ function cgen_vhdl_package()
end
end
emit
(
"return tmp;"
);
indent_left
();
emit
(
"end function;"
);
indent_left
();
emit
(
""
);
emit
(
"end package body;"
);
end
...
...
@@ -212,8 +168,8 @@ function cgen_vhdl_port_struct(direction)
emit
(
line
);
end
indent_left
();
emit
(
"end record;"
);
indent_left
();
emit
(
""
);
emit
(
"constant c_"
..
periph
.
hdl_prefix
..
"_"
..
direction
..
"_registers_init_value: t_"
..
periph
.
hdl_prefix
..
"_"
..
direction
..
"_registers := ("
);
indent_right
();
...
...
@@ -232,8 +188,7 @@ function cgen_vhdl_port_struct(direction)
emit
(
line
);
end
indent_left
();
emit
(
");"
);
emit
(
");"
);
end
...
...
@@ -264,15 +219,20 @@ function cgen_vhdl_header(file_name)
emit
(
"use work.wbgen2_pkg.all;"
);
end
if
(
options
.
hdl_reg_style
==
"record_full"
)
then
emit
(
"use work.wishbone_pkg.all;"
);
end
emit
(
""
);
end
function
cgen_vhdl_interface_declaration
(
keyword
)
emit
(
keyword
..
" "
..
periph
.
hdl_entity
..
" is"
);
-- function generates VHDL entity header (ports and generics) and beginning of ARCHITECTURE block (signal and constant definitions).
function
cgen_vhdl_entity
()
local
last
;
if
(
options
.
hdl_reg_style
==
"record"
)
then
emit
(
"use work."
..
periph
.
hdl_prefix
..
"_wbgen2_pkg.all;"
);
emit
(
"
\n
"
);
end
emit
(
"entity "
..
periph
.
hdl_entity
..
" is"
);
indent_right
();
if
(
table
.
getn
(
g_optlist
)
~=
0
)
then
...
...
@@ -302,15 +262,7 @@ function cgen_vhdl_interface_declaration(keyword)
for
i
=
1
,
table
.
getn
(
g_portlist
)
do
local
port
=
g_portlist
[
i
];
local
generate
=
true
;
if
(
options
.
hdl_reg_style
==
"record"
and
port
.
is_reg_port
)
then
generate
=
false
;
elseif
(
options
.
hdl_reg_style
==
"record_full"
and
(
port
.
is_reg_port
or
port
.
is_wb
)
)
then
generate
=
false
;
end
if
(
generate
)
then
if
(
options
.
hdl_reg_style
==
"signals"
or
not
port
.
is_reg_port
)
then
-- if we have a comment associated with current port, let's emit it before the port definition.
if
(
port
.
comment
~=
nil
and
port
.
comment
~=
""
)
then
...
...
@@ -326,50 +278,24 @@ function cgen_vhdl_interface_declaration(keyword)
end
-- eventually append a semicolon
line
=
line
..
csel
((
i
==
table
.
getn
(
g_portlist
))
and
not
(
options
.
hdl_reg_style
==
"record"
or
options
.
hdl_reg_style
==
"record_full"
),
""
,
";"
);
line
=
line
..
csel
((
i
==
table
.
getn
(
g_portlist
))
and
not
(
options
.
hdl_reg_style
==
"record"
),
""
,
";"
);
-- and spit out the line
emit
(
line
);
end
end
if
(
options
.
hdl_reg_style
==
"record_full"
)
then
emit
(
string.format
(
"%-40s : %-6s %s;"
,
"slave_i"
,
"in"
,
"t_wishbone_slave_in"
));
emit
(
string.format
(
"%-40s : %-6s %s;"
,
"slave_o"
,
"out"
,
"t_wishbone_slave_out"
));
emit
(
string.format
(
"%-40s : %-6s %s;"
,
"int_o"
,
"out"
,
"std_logic"
));
if
(
options
.
hdl_reg_style
==
"record"
)
then
emit
(
string.format
(
"%-40s : %-6s %s"
,
"regs_i"
,
"in"
,
"t_"
..
periph
.
hdl_prefix
..
"_in_registers;"
));
emit
(
string.format
(
"%-40s : %-6s %s"
,
"regs_o"
,
"out"
,
"t_"
..
periph
.
hdl_prefix
..
"_out_registers"
));
end
if
(
options
.
hdl_reg_style
==
"record"
or
options
.
hdl_reg_style
==
"record_full"
)
then
emit
(
string.format
(
"%-40s : %-6s %s;"
,
"regs_i"
,
"in"
,
"t_"
..
periph
.
hdl_prefix
..
"_in_registers"
));
emit
(
string.format
(
"%-40s : %-6s %s"
,
"regs_o"
,
"out"
,
"t_"
..
periph
.
hdl_prefix
..
"_out_registers"
));
end
indent_left
();
emit
(
");"
);
indent_left
();
if
(
keyword
==
"component"
)
then
emit
(
"end component;"
);
else
emit
(
"end "
..
periph
.
hdl_entity
..
";"
);
end
emit
(
"end "
..
periph
.
hdl_entity
..
";"
);
emit
(
""
);
end
-- function generates VHDL entity header (ports and generics) and beginning of ARCHITECTURE block (signal and constant definitions).
function
cgen_vhdl_entity
()
local
last
;
if
(
options
.
hdl_reg_style
==
"record"
or
options
.
hdl_reg_style
==
"record_full"
)
then
emit
(
"use work."
..
get_pkg_name
()
..
".all;"
);
emit
(
"
\n
"
);
end
cgen_vhdl_interface_declaration
(
"entity"
)
-- generate the ARCHITECTURE block with signal definitions
emit
(
"architecture syn of "
..
periph
.
hdl_entity
..
" is"
);
...
...
@@ -927,7 +853,7 @@ function cgen_generate_vhdl_code(tree)
end
end
if
(
(
options
.
hdl_reg_style
==
"record"
or
options
.
hdl_reg_style
==
"record_full"
)
and
options
.
output_package_file
~=
nil
)
then
if
(
options
.
hdl_reg_style
==
"record"
and
options
.
output_package_file
~=
nil
)
then
cgen_generate_init
(
options
.
output_package_file
);
cgen_new_snippet
();
cgen_vhdl_header
(
options
.
output_package_file
);
...
...
wbgen_regbank.lua
View file @
69883c7c
...
...
@@ -377,6 +377,10 @@ function gen_hdl_code_slv(field, reg)
field
.
ackgen_code_pre
=
{
va
(
prefix
..
"_load_o"
,
0
);};
field
.
ackgen_code
=
{
va
(
prefix
..
"_load_o"
,
0
);
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_load_o"
,
0
);
};
elseif
(
field
.
access
==
ACC_WO_RO
)
then
die
(
"WO-RO type unsupported yet ("
..
field
.
name
..
")"
);
end
else
-- asynchronous register. Even tougher shit :(
...
...
Dimitris Lampridis
@dlampridis
mentioned in commit
cbc9b2bc
·
Sep 26, 2019
mentioned in commit
cbc9b2bc
mentioned in commit cbc9b2bcf4d18bca74e558a2dcd20786d47487f6
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