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W
Wishbone slave generator
Commit 53807e02 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Partially revert cc5a5c00. 

Some of the signals dropped in commit cc5a5c00 were actually being used when generating RAMs.

They have been reintroduced, but this time only when generating RAMs.
parent 307440ab
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Showing with 328 additions and 280 deletions
target_pipelined_wb.lua
View file @ 53807e02
...@@ -47,8 +47,14 @@ local width = math.max(1, address_bus_width); ...@@ -47,8 +47,14 @@ local width = math.max(1, address_bus_width);
local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"), local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"),
signal(SLV, DATA_BUS_WIDTH, "rddata_reg"), signal(SLV, DATA_BUS_WIDTH, "rddata_reg"),
signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"), signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"),
signal(SLV, DATA_BUS_WIDTH/8 , "bwsel_reg"),
signal(SLV, width, "rwaddr_reg"), signal(SLV, width, "rwaddr_reg"),
signal(BIT, 0, "ack_in_progress") signal(BIT, 0, "ack_in_progress"),
signal(BIT, 0, "wr_int"),
signal(BIT, 0, "rd_int"),
signal(SLV, DATA_BUS_WIDTH, "allones"),
signal(SLV, DATA_BUS_WIDTH, "allzeros")
}; };
add_global_signals(wb_sigs); add_global_signals(wb_sigs);
...@@ -207,6 +213,17 @@ function gen_bus_logic_pipelined_wb(mode) ...@@ -207,6 +213,17 @@ function gen_bus_logic_pipelined_wb(mode)
-- we have some RAMs in our slave? -- we have some RAMs in our slave?
if(periph.ramcount > 0) then if(periph.ramcount > 0) then
local ram_signals_code = {
vcomment("Some internal signals assignments used by RAMs.");
va("bwsel_reg", "wb_sel_i");
va("rd_int", vand("wb_cyc_i", vand("wb_stb_i", vnot("wb_we_i"))));
va("wr_int", vand("wb_cyc_i", vand("wb_stb_i", "wb_we_i")));
va("allones", vothers(1));
va("allzeros", vothers(0));
};
table_join(code, ram_signals_code);
-- the data output is muxed between RAMs and register bank. Here we generate a combinatorial mux if we don't want the output to be registered. This gives us -- the data output is muxed between RAMs and register bank. Here we generate a combinatorial mux if we don't want the output to be registered. This gives us
-- memory access time of 2 clock cycles. Otherwise the ram output is handled by the main process. -- memory access time of 2 clock cycles. Otherwise the ram output is handled by the main process.
if(not options.register_data_output) then if(not options.register_data_output) then
......
target_wishbone.lua
View file @ 53807e02
...@@ -39,9 +39,15 @@ local width = math.max(1, address_bus_width); ...@@ -39,9 +39,15 @@ local width = math.max(1, address_bus_width);
local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"), local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"),
signal(SLV, DATA_BUS_WIDTH, "rddata_reg"), signal(SLV, DATA_BUS_WIDTH, "rddata_reg"),
signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"), signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"),
signal(SLV, DATA_BUS_WIDTH/8 , "bwsel_reg"),
signal(SLV, width, "rwaddr_reg"), signal(SLV, width, "rwaddr_reg"),
signal(BIT, 0, "ack_in_progress"), signal(BIT, 0, "ack_in_progress"),
signal(BIT, 0, "bus_clock_int") signal(BIT, 0, "wr_int"),
signal(BIT, 0, "rd_int"),
signal(BIT, 0, "bus_clock_int"),
signal(SLV, DATA_BUS_WIDTH, "allones"),
signal(SLV, DATA_BUS_WIDTH, "allzeros")
}; };
add_global_signals(wb_sigs); add_global_signals(wb_sigs);
...@@ -201,6 +207,17 @@ function gen_bus_logic_wishbone() ...@@ -201,6 +207,17 @@ function gen_bus_logic_wishbone()
-- we have some RAMs in our slave? -- we have some RAMs in our slave?
if(periph.ramcount > 0) then if(periph.ramcount > 0) then
local ram_signals_code = {
vcomment("Some internal signals assignments used by RAMs.");
va("bwsel_reg", "wb_sel_i");
va("rd_int", vand("wb_cyc_i", vand("wb_stb_i", vnot("wb_we_i"))));
va("wr_int", vand("wb_cyc_i", vand("wb_stb_i", "wb_we_i")));
va("allones", vothers(1));
va("allzeros", vothers(0));
};
table_join(code, ram_signals_code);
-- the data output is muxed between RAMs and register bank. Here we generate a combinatorial mux if we don't want the output to be registered. This gives us -- the data output is muxed between RAMs and register bank. Here we generate a combinatorial mux if we don't want the output to be registered. This gives us
-- memory access time of 2 clock cycles. Otherwise the ram output is handled by the main process. -- memory access time of 2 clock cycles. Otherwise the ram output is handled by the main process.
if(not options.register_data_output) then if(not options.register_data_output) then
......
wbgen2
View file @ 53807e02
#!/usr/bin/env lua #!/usr/bin/env lua
package.preload['alt_getopt']=(function(...) package.preload['alt_getopt']=(function(...)
local i,s,u,a,o=type,pairs,ipairs,io,os local i,r,u,a,o=type,pairs,ipairs,io,os
module("alt_getopt") module("alt_getopt")
local function r(t) local function c(t)
local e=1 local e=1
local e=#t local e=#t
local e={} local e={}
for t,a in t:gmatch("(%w)(:?)")do for a,t in t:gmatch("(%w)(:?)")do
e[t]=#a e[a]=#t
end end
return e return e
end end
...@@ -31,13 +31,13 @@ end ...@@ -31,13 +31,13 @@ end
end end
return e return e
end end
function get_ordered_opts(n,o,a) function get_ordered_opts(n,a,s)
local t=1 local t=1
local e=1 local e=1
local i={} local i={}
local h={} local h={}
local o=r(o) local o=c(a)
for e,t in s(a)do for e,t in r(s)do
o[e]=t o[e]=t
end end
while t<=#n do while t<=#n do
...@@ -176,22 +176,22 @@ die(t.." expected."); ...@@ -176,22 +176,22 @@ die(t.." expected.");
end end
return e; return e;
end end
function range2bits(t) function range2bits(e)
local e=t[1]; local t=e[1];
local a=t[2]; local a=e[2];
local t; local e;
if(math.abs(e)>math.abs(a))then if(math.abs(t)>math.abs(a))then
t=math.abs(e); e=math.abs(t);
else else
t=math.abs(a); e=math.abs(a);
end end
local t=math.ceil(math.log(t)/math.log(2)); local e=math.ceil(math.log(e)/math.log(2));
if(e<0)then if(t<0)then
t=t+1; e=e+1;
end end
return t; return e;
end end
function calc_size(e,a) function calc_size(e,t)
if(e.type==MONOSTABLE or e.type==BIT)then if(e.type==MONOSTABLE or e.type==BIT)then
e.size=1; e.size=1;
elseif(e.type==SLV or e.type==PASS_THROUGH)then elseif(e.type==SLV or e.type==PASS_THROUGH)then
...@@ -212,7 +212,7 @@ end ...@@ -212,7 +212,7 @@ end
elseif(e.type==ENUM)then elseif(e.type==ENUM)then
die("ENUM-type fields are not yet supported. Sorry :("); die("ENUM-type fields are not yet supported. Sorry :(");
end end
a.total_size=a.total_size+e.size; t.total_size=t.total_size+e.size;
end end
function foreach_reg(a,t,e) function foreach_reg(a,t,e)
if(e==nil)then if(e==nil)then
...@@ -254,27 +254,27 @@ end ...@@ -254,27 +254,27 @@ end
print("Align ",e.name,e.align,o,a); print("Align ",e.name,e.align,o,a);
return a; return a;
end end
function calc_field_offset(e,t) function calc_field_offset(t,e)
local a=t.current_offset; local a=e.current_offset;
if(t.__type==TYPE_FIFO)then if(e.__type==TYPE_FIFO)then
local o=align(e,a); local o=align(t,a);
if((o%DATA_BUS_WIDTH)+e.size>DATA_BUS_WIDTH)then if((o%DATA_BUS_WIDTH)+t.size>DATA_BUS_WIDTH)then
e.align=DATA_BUS_WIDTH; t.align=DATA_BUS_WIDTH;
a=align(e,a); a=align(t,a);
else else
a=o; a=o;
end end
t.current_offset=a+e.size; e.current_offset=a+t.size;
e.offset=a; t.offset=a;
else else
a=align(e,a); a=align(t,a);
t.current_offset=a+e.size; e.current_offset=a+t.size;
e.offset=a; t.offset=a;
end end
e.offset_unaligned=t.current_offset_unaligned; t.offset_unaligned=e.current_offset_unaligned;
t.current_offset_unaligned=t.current_offset_unaligned+e.size; e.current_offset_unaligned=e.current_offset_unaligned+t.size;
if(t.__type==TYPE_REG and t.current_offset>DATA_BUS_WIDTH)then if(e.__type==TYPE_REG and e.current_offset>DATA_BUS_WIDTH)then
die("Total size of register '"..t.name.."' ("..t.current_offset..") exceeds data bus width ("..DATA_BUS_WIDTH..")"); die("Total size of register '"..e.name.."' ("..e.current_offset..") exceeds data bus width ("..DATA_BUS_WIDTH..")");
end end
end end
function calc_num_fields(t,e) function calc_num_fields(t,e)
...@@ -296,11 +296,11 @@ function inset(e,t) ...@@ -296,11 +296,11 @@ function inset(e,t)
for a,t in ipairs(t)do if(e==t)then return true;end end for a,t in ipairs(t)do if(e==t)then return true;end end
return false; return false;
end end
function csel(e,a,t) function csel(a,t,e)
if(e)then if(a)then
return a;
else
return t; return t;
else
return e;
end end
end end
function check_field_types(e) function check_field_types(e)
...@@ -404,25 +404,25 @@ end ...@@ -404,25 +404,25 @@ end
function assign_addresses() function assign_addresses()
local o=math.max(max_ram_addr_bits,log2up(all_regs_size)); local o=math.max(max_ram_addr_bits,log2up(all_regs_size));
local e=num_rams; local e=num_rams;
local t=0; local a=0;
if(all_regs_size>0)then if(all_regs_size>0)then
e=e+1; e=e+1;
end end
local a=log2up(e); local t=log2up(e);
foreach_reg({TYPE_REG,TYPE_FIFO},function(e) foreach_reg({TYPE_REG,TYPE_FIFO},function(e)
if(e.__type==TYPE_REG)then if(e.__type==TYPE_REG)then
e.base=align(e,t); e.base=align(e,a);
t=e.base+1; a=e.base+1;
end end
end); end);
address_bus_width=o+a; address_bus_width=o+t;
address_bus_select_bits=a; address_bus_select_bits=t;
end end
function find_max(e,t) function find_max(e,a)
local a=0; local t=0;
local o,o; local o,o;
for o,e in pairs(e)do if(type(e)=='table'and e[t]~=nil and e[t]>a)then a=e[t];end end for o,e in pairs(e)do if(type(e)=='table'and e[a]~=nil and e[a]>t)then t=e[a];end end
return a; return t;
end end
function table_join(t,e) function table_join(t,e)
local a,a; local a,a;
...@@ -453,7 +453,7 @@ end); ...@@ -453,7 +453,7 @@ end);
end); end);
return t; return t;
end end
function remove_duplicates(o) function remove_duplicates(a)
function count_entries(t,a) function count_entries(t,a)
local o,o,e; local o,o,e;
e=0; e=0;
...@@ -461,7 +461,7 @@ for o,t in ipairs(t)do if(t==a)then e=e+1;end end ...@@ -461,7 +461,7 @@ for o,t in ipairs(t)do if(t==a)then e=e+1;end end
return e; return e;
end end
local e={}; local e={};
for a,t in ipairs(o)do for a,t in ipairs(a)do
local a=count_entries(e,t); local a=count_entries(e,t);
if(a==0)then if(a==0)then
table.insert(e,t); table.insert(e,t);
...@@ -487,72 +487,72 @@ die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, ...@@ -487,72 +487,72 @@ die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs,
end end
end end
function deepcopy(i) function deepcopy(i)
local a={} local o={}
local function t(e) local function t(e)
if type(e)~="table"then if type(e)~="table"then
return e return e
elseif a[e]then elseif o[e]then
return a[e] return o[e]
end end
local o={} local a={}
a[e]=o o[e]=a
for a,e in pairs(e)do for e,o in pairs(e)do
o[t(a)]=t(e) a[t(e)]=t(o)
end end
return setmetatable(o,getmetatable(e)) return setmetatable(a,getmetatable(e))
end end
return t(i) return t(i)
end end
function va(t,a) function va(a,t)
local e={}; local e={};
e.t="assign"; e.t="assign";
e.dst=t; e.dst=a;
e.src=a; e.src=t;
return e; return e;
end end
function vi(a,o,t) function vi(a,t,o)
local e={}; local e={};
e.t="index"; e.t="index";
e.name=a; e.name=a;
e.h=o; e.h=t;
e.l=t; e.l=o;
return e; return e;
end end
function vinstance(o,t,a) function vinstance(t,o,a)
local e={}; local e={};
e.t="instance"; e.t="instance";
e.name=o; e.name=t;
e.component=t; e.component=o;
e.maps=a; e.maps=a;
return e; return e;
end end
function vpm(a,t) function vpm(t,a)
local e={}; local e={};
e.t="portmap"; e.t="portmap";
e.to=a; e.to=t;
e.from=t; e.from=a;
return e; return e;
end end
function vgm(t,a) function vgm(a,t)
local e={}; local e={};
e.t="genmap"; e.t="genmap";
e.to=t; e.to=a;
e.from=a; e.from=t;
return e; return e;
end end
function vcombprocess(t,a) function vcombprocess(a,t)
local e={}; local e={};
e.t="combprocess"; e.t="combprocess";
e.slist=t; e.slist=a;
e.code=a; e.code=t;
return e; return e;
end end
function vsyncprocess(t,a,o) function vsyncprocess(t,o,a)
local e={}; local e={};
e.t="syncprocess"; e.t="syncprocess";
e.clk=t; e.clk=t;
e.rst=a; e.rst=o;
e.code=o; e.code=a;
return e; return e;
end end
function vreset(a,t) function vreset(a,t)
...@@ -568,11 +568,11 @@ e.t="posedge"; ...@@ -568,11 +568,11 @@ e.t="posedge";
e.code=t; e.code=t;
return e; return e;
end end
function vif(a,t,o) function vif(t,a,o)
local e={}; local e={};
e.t="if"; e.t="if";
e.cond={a}; e.cond={t};
e.code=t; e.code=a;
e.code_else=o; e.code_else=o;
return e; return e;
end end
...@@ -583,18 +583,18 @@ e.cond={t}; ...@@ -583,18 +583,18 @@ e.cond={t};
e.code=a; e.code=a;
return e; return e;
end end
function vequal(t,a) function vequal(a,t)
local e={}; local e={};
e.t="eq"; e.t="eq";
e.a=t; e.a=a;
e.b=a; e.b=t;
return e; return e;
end end
function vand(a,t) function vand(t,a)
local e={}; local e={};
e.t="and"; e.t="and";
e.a=a; e.a=t;
e.b=t; e.b=a;
return e; return e;
end end
function vor(a,t) function vor(a,t)
...@@ -659,12 +659,12 @@ local e={} ...@@ -659,12 +659,12 @@ local e={}
e.t="undefined"; e.t="undefined";
return e; return e;
end end
function signal(o,a,t,i) function signal(o,a,i,t)
local e={} local e={}
e.comment=i; e.comment=t;
e.type=o; e.type=o;
e.range=a; e.range=a;
e.name=t; e.name=i;
return e; return e;
end end
VPORT_WB=1; VPORT_WB=1;
...@@ -736,12 +736,12 @@ end ...@@ -736,12 +736,12 @@ end
function cgen_build_optional_list() function cgen_build_optional_list()
local o={} local o={}
local a={} local a={}
local t=1 local e=1
for i,e in pairs(tree_2_table("optional"))do for i,t in pairs(tree_2_table("optional"))do
if o[e]==nil then if o[t]==nil then
o[e]=1 o[t]=1
a[t]=e a[e]=t
t=t+1 e=e+1
end end
end end
return a return a
...@@ -955,15 +955,15 @@ indent_left(); ...@@ -955,15 +955,15 @@ indent_left();
emit(""); emit("");
emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := ("); emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := (");
indent_right(); indent_right();
for t=1,table.getn(a)do for e=1,table.getn(a)do
local e=a[t]; local t=a[e];
line=strip_periph_prefix(e.name).." => "; line=strip_periph_prefix(t.name).." => ";
if(e.range>1)then if(t.range>1)then
line=line.."(others => '0')" line=line.."(others => '0')"
else else
line=line.."'0'" line=line.."'0'"
end end
if(t~=table.getn(a))then if(e~=table.getn(a))then
line=line..","; line=line..",";
end end
emit(line); emit(line);
...@@ -1754,23 +1754,23 @@ end ...@@ -1754,23 +1754,23 @@ end
function cgen_verilog_openpin(e) function cgen_verilog_openpin(e)
emitx(""); emitx("");
end end
function cgen_verilog_combprocess(t) function cgen_verilog_combprocess(e)
local e=true; local t=true;
emiti(); emiti();
emitx("always @("); emitx("always @(");
a=true; a=true;
for a,t in pairs(t.slist)do for a,e in pairs(e.slist)do
if(e)then if(t)then
e=false; t=false;
else else
emitx(" or "); emitx(" or ");
end end
emitx(t); emitx(e);
end end
emit(")"); emit(")");
emit("begin"); emit("begin");
indent_right(); indent_right();
recurse(t.code); recurse(e.code);
indent_left(); indent_left();
a=false; a=false;
emit("end"); emit("end");
...@@ -2219,7 +2219,7 @@ local e=periph.description; ...@@ -2219,7 +2219,7 @@ local e=periph.description;
if(e==nil)then e="";end if(e==nil)then e="";end
emit('<p>'..string.gsub(e,"\n","<br>")..'</p>'); emit('<p>'..string.gsub(e,"\n","<br>")..'</p>');
emit('<h3>Contents:</h3>'); emit('<h3>Contents:</h3>');
table.sort(doc_toc,function(t,e)return t.key<e.key;end); table.sort(doc_toc,function(e,t)return e.key<t.key;end);
for t,e in ipairs(doc_toc)do for t,e in ipairs(doc_toc)do
emit('<span style="margin-left: '..((e.level-1)*20)..'px; ">'..e.id.." "..hlink('#'..e.id_mangled,e.name)..'</span><br/>'); emit('<span style="margin-left: '..((e.level-1)*20)..'px; ">'..e.id.." "..hlink('#'..e.id_mangled,e.name)..'</span><br/>');
end end
...@@ -2274,10 +2274,10 @@ end ...@@ -2274,10 +2274,10 @@ end
end); end);
htable_emit(o); htable_emit(o);
end end
function find_field_by_offset(e,t) function find_field_by_offset(e,a)
local a=nil; local t=nil;
foreach_subfield(e,function(e)if(t>=e.offset and t<=(e.offset+e.size-1))then a=e;end end); foreach_subfield(e,function(e)if(a>=e.offset and a<=(e.offset+e.size-1))then t=e;end end);
return a; return t;
end end
function cgen_doc_fieldtable(h,i) function cgen_doc_fieldtable(h,i)
local e=70; local e=70;
...@@ -2439,11 +2439,11 @@ emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>"); ...@@ -2439,11 +2439,11 @@ emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end end
end end
function cgen_generate_html_documentation() function cgen_generate_html_documentation()
cgen_new_snippet();cgen_doc_hdl_symbol();local i=cgen_get_snippet(); cgen_new_snippet();cgen_doc_hdl_symbol();local o=cgen_get_snippet();
cgen_new_snippet(); cgen_new_snippet();
emit(hsection(3,0,"Register description")); emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end); foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local o=cgen_get_snippet(); local i=cgen_get_snippet();
local t=""; local t="";
if(periph.ramcount>0)then if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks")); emit(hsection(4,0,"Memory blocks"));
...@@ -2464,8 +2464,8 @@ local e=cgen_get_snippet(); ...@@ -2464,8 +2464,8 @@ local e=cgen_get_snippet();
cgen_new_snippet(); cgen_new_snippet();
cgen_doc_header_and_toc(); cgen_doc_header_and_toc();
emit(e); emit(e);
emit(i);
emit(o); emit(o);
emit(i);
emit(t); emit(t);
emit(a); emit(a);
emit('</BODY>'); emit('</BODY>');
...@@ -2886,19 +2886,19 @@ cgen_new_snippet(); ...@@ -2886,19 +2886,19 @@ cgen_new_snippet();
emit("\\subsubsection{Register description}"); emit("\\subsubsection{Register description}");
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_reg(e);end end); foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_reg(e);end end);
local o=cgen_get_snippet(); local o=cgen_get_snippet();
local t=""; local a="";
if(periph.ramcount>0)then if(periph.ramcount>0)then
emit("\\subsubsection{Memory blocks}"); emit("\\subsubsection{Memory blocks}");
cgen_new_snippet(); cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_ram(e);end end); foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_ram(e);end end);
t=cgen_get_snippet(); a=cgen_get_snippet();
end end
local a=""; local t="";
if(periph.irqcount>0)then if(periph.irqcount>0)then
cgen_new_snippet(); cgen_new_snippet();
emit("\\subsubsection{Interrupts}"); emit("\\subsubsection{Interrupts}");
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_irq(e);end end); foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_irq(e);end end);
a=cgen_get_snippet(); t=cgen_get_snippet();
end end
cgen_new_snippet(); cgen_new_snippet();
cgen_doc_lx_memmap(); cgen_doc_lx_memmap();
...@@ -2907,8 +2907,8 @@ cgen_new_snippet(); ...@@ -2907,8 +2907,8 @@ cgen_new_snippet();
cgen_doc_lx_header_and_toc(); cgen_doc_lx_header_and_toc();
emit(e); emit(e);
emit(o); emit(o);
emit(t);
emit(a); emit(a);
emit(t);
cgen_write_current_snippet(); cgen_write_current_snippet();
end end
function gen_hdl_field_prefix(a,e) function gen_hdl_field_prefix(a,e)
...@@ -2984,163 +2984,163 @@ t.ackgen_code_pre={va(e.."_int",e.."_int_delay"); ...@@ -2984,163 +2984,163 @@ t.ackgen_code_pre={va(e.."_int",e.."_int_delay");
va(e.."_int_delay",0);}; va(e.."_int_delay",0);};
end end
end end
function gen_hdl_code_bit(e,a) function gen_hdl_code_bit(t,a)
local t=gen_hdl_field_prefix(e,a); local e=gen_hdl_field_prefix(t,a);
e.prefix=t; t.prefix=e;
if(e.clock==nil)then if(t.clock==nil)then
if(e.access==ACC_RW_RO)then if(t.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)}; t.ports={port(BIT,0,"out",e.."_o","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int")}; t.signals={signal(BIT,0,e.."_int")};
e.acklen=1; t.acklen=1;
e.write_code={ t.write_code={
va(t.."_int",vi("wrdata_reg",e.offset))}; va(e.."_int",vi("wrdata_reg",t.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")}; t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))}; t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
e.extra_code={va(t.."_o",t.."_int")}; t.extra_code={va(e.."_o",e.."_int")};
elseif(e.access==ACC_RO_WO)then elseif(t.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)}; t.ports={port(BIT,0,"in",e.."_i","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={}; t.signals={};
e.acklen=1; t.acklen=1;
e.write_code={}; t.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")}; t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
e.reset_code_main={}; t.reset_code_main={};
e.extra_code={}; t.extra_code={};
elseif(e.access==ACC_WO_RO)then elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")"); die("WO-RO type unsupported yet ("..t.name..")");
elseif(e.access==ACC_RW_RW)then elseif(t.access==ACC_RW_RW)then
if(e.load==LOAD_EXT)then if(t.load==LOAD_EXT)then
e.ports={port(BIT,0,"out",t.."_o","Ports for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG), t.ports={port(BIT,0,"out",e.."_o","Ports for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG), port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)}; port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
e.acklen=1; t.acklen=1;
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")}; t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
e.write_code={ t.write_code={
va(t.."_load_o",1)}; va(e.."_load_o",1)};
e.extra_code={va(t.."_o",vi("wrdata_reg",e.offset))}; t.extra_code={va(e.."_o",vi("wrdata_reg",t.offset))};
e.ackgen_code_pre={va(t.."_load_o",0)}; t.ackgen_code_pre={va(e.."_load_o",0)};
e.ackgen_code={va(t.."_load_o",0)}; t.ackgen_code={va(e.."_load_o",0)};
e.reset_code_main={va(t.."_load_o",0)}; t.reset_code_main={va(e.."_load_o",0)};
else else
die("internal RW/RW register storage unsupported yet ("..e.name..")"); die("internal RW/RW register storage unsupported yet ("..t.name..")");
end end
end end
else else
if(e.access==ACC_RW_RO)then if(t.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)}; t.ports={port(BIT,0,"out",e.."_o","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int"), t.signals={signal(BIT,0,e.."_int"),
signal(BIT,0,t.."_sync0"), signal(BIT,0,e.."_sync0"),
signal(BIT,0,t.."_sync1")}; signal(BIT,0,e.."_sync1")};
e.acklen=4; t.acklen=4;
e.write_code={va(t.."_int",vi("wrdata_reg",e.offset))}; t.write_code={va(e.."_int",vi("wrdata_reg",t.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")}; t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))}; t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RW/RO, clk_sys_i <-> "..e.clock..")"); t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RW/RO, clk_sys_i <-> "..t.clock..")");
vsyncprocess(e.clock,"rst_n_i",{ vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{ vreset(0,{
va(t.."_o",csel(e.reset_value==nil,0,e.reset_value)); va(e.."_o",csel(t.reset_value==nil,0,t.reset_value));
va(t.."_sync0",csel(e.reset_value==nil,0,e.reset_value)); va(e.."_sync0",csel(t.reset_value==nil,0,t.reset_value));
va(t.."_sync1",csel(e.reset_value==nil,0,e.reset_value)); va(e.."_sync1",csel(t.reset_value==nil,0,t.reset_value));
}); });
vposedge({ vposedge({
va(t.."_sync0",t.."_int"); va(e.."_sync0",e.."_int");
va(t.."_sync1",t.."_sync0"); va(e.."_sync1",e.."_sync0");
va(t.."_o",t.."_sync1"); va(e.."_o",e.."_sync1");
}); });
}); });
}; };
elseif(e.access==ACC_RO_WO)then elseif(t.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)}; t.ports={port(BIT,0,"in",e.."_i","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_sync0"), t.signals={signal(BIT,0,e.."_sync0"),
signal(BIT,0,t.."_sync1")}; signal(BIT,0,e.."_sync1")};
e.acklen=1; t.acklen=1;
e.write_code={}; t.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_sync1")}; t.read_code={va(vi("rddata_reg",t.offset),e.."_sync1")};
e.reset_code_main={}; t.reset_code_main={};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RO/WO, "..e.clock.." -> clk_sys_i)"); t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RO/WO, "..t.clock.." -> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{ vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{ vreset(0,{
va(t.."_sync0",0); va(e.."_sync0",0);
va(t.."_sync1",0); va(e.."_sync1",0);
}); });
vposedge({ vposedge({
va(t.."_sync0",t.."_i"); va(e.."_sync0",e.."_i");
va(t.."_sync1",t.."_sync0"); va(e.."_sync1",e.."_sync0");
}); });
}); });
}; };
elseif(e.access==ACC_RW_RW)then elseif(t.access==ACC_RW_RW)then
if(e.load~=LOAD_EXT)then if(t.load~=LOAD_EXT)then
die("Only external load is supported for RW/RW bit fields"); die("Only external load is supported for RW/RW bit fields");
end end
local a="Ports for asynchronous (clock: "..e.clock..") RW/RW BIT field: '"..e.name.."' in reg: '"..a.name.."'"; local a="Ports for asynchronous (clock: "..t.clock..") RW/RW BIT field: '"..t.name.."' in reg: '"..a.name.."'";
e.ports={port(BIT,0,"out",t.."_o",a,VPORT_REG), t.ports={port(BIT,0,"out",e.."_o",a,VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG), port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)}; port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
e.signals={signal(BIT,0,t.."_int_read"), t.signals={signal(BIT,0,e.."_int_read"),
signal(BIT,0,t.."_int_write"), signal(BIT,0,e.."_int_write"),
signal(BIT,0,t.."_lw"), signal(BIT,0,e.."_lw"),
signal(BIT,0,t.."_lw_delay"), signal(BIT,0,e.."_lw_delay"),
signal(BIT,0,t.."_lw_read_in_progress"), signal(BIT,0,e.."_lw_read_in_progress"),
signal(BIT,0,t.."_lw_s0"), signal(BIT,0,e.."_lw_s0"),
signal(BIT,0,t.."_lw_s1"), signal(BIT,0,e.."_lw_s1"),
signal(BIT,0,t.."_lw_s2"), signal(BIT,0,e.."_lw_s2"),
signal(BIT,0,t.."_rwsel")}; signal(BIT,0,e.."_rwsel")};
e.acklen=6; t.acklen=6;
e.write_code={ t.write_code={
va(t.."_int_write",vi("wrdata_reg",e.offset)); va(e.."_int_write",vi("wrdata_reg",t.offset));
va(t.."_lw",1); va(e.."_lw",1);
va(t.."_lw_delay",1); va(e.."_lw_delay",1);
va(t.."_lw_read_in_progress",0); va(e.."_lw_read_in_progress",0);
va(t.."_rwsel",1);}; va(e.."_rwsel",1);};
e.read_code={vif(vequal("wb_we_i",0),{ t.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",e.offset),vundefined()); va(vi("rddata_reg",t.offset),vundefined());
va(t.."_lw",1); va(e.."_lw",1);
va(t.."_lw_delay",1); va(e.."_lw_delay",1);
va(t.."_lw_read_in_progress",1); va(e.."_lw_read_in_progress",1);
va(t.."_rwsel",0);});}; va(e.."_rwsel",0);});};
e.reset_code_main={va(t.."_lw",0); t.reset_code_main={va(e.."_lw",0);
va(t.."_lw_delay",0); va(e.."_lw_delay",0);
va(t.."_lw_read_in_progress",0); va(e.."_lw_read_in_progress",0);
va(t.."_rwsel",0); va(e.."_rwsel",0);
va(t.."_int_write",0); va(e.."_int_write",0);
}; };
e.ackgen_code_pre={va(t.."_lw",t.."_lw_delay"); t.ackgen_code_pre={va(e.."_lw",e.."_lw_delay");
va(t.."_lw_delay",0); va(e.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(t.."_lw_read_in_progress",1)),{ vif(vand(vequal(vi("ack_sreg",1),1),vequal(e.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",e.offset),t.."_int_read"); va(vi("rddata_reg",t.offset),e.."_int_read");
va(t.."_lw_read_in_progress",0); va(e.."_lw_read_in_progress",0);
}); });
}; };
e.extra_code={vcomment("asynchronous BIT register : "..e.name.." (type RW/WO, "..e.clock.." <-> clk_sys_i)"); t.extra_code={vcomment("asynchronous BIT register : "..t.name.." (type RW/WO, "..t.clock.." <-> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{ vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{ vreset(0,{
va(t.."_lw_s0",0); va(e.."_lw_s0",0);
va(t.."_lw_s1",0); va(e.."_lw_s1",0);
va(t.."_lw_s2",0); va(e.."_lw_s2",0);
va(t.."_int_read",0); va(e.."_int_read",0);
va(t.."_load_o",0); va(e.."_load_o",0);
va(t.."_o",0); va(e.."_o",0);
}); });
vposedge({ vposedge({
va(t.."_lw_s0",t.."_lw"); va(e.."_lw_s0",e.."_lw");
va(t.."_lw_s1",t.."_lw_s0"); va(e.."_lw_s1",e.."_lw_s0");
va(t.."_lw_s2",t.."_lw_s1"); va(e.."_lw_s2",e.."_lw_s1");
vif(vand(vequal(t.."_lw_s2",0),vequal(t.."_lw_s1",1)),{ vif(vand(vequal(e.."_lw_s2",0),vequal(e.."_lw_s1",1)),{
vif(vequal(t.."_rwsel",1),{ vif(vequal(e.."_rwsel",1),{
va(t.."_o",t.."_int_write"); va(e.."_o",e.."_int_write");
va(t.."_load_o",1); va(e.."_load_o",1);
},{ },{
va(t.."_load_o",0); va(e.."_load_o",0);
va(t.."_int_read",t.."_i"); va(e.."_int_read",e.."_i");
}); });
},{ },{
va(t.."_load_o",0); va(e.."_load_o",0);
}); });
}); });
}); });
}; };
elseif(e.access==ACC_WO_RO)then elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")"); die("WO-RO type unsupported yet ("..t.name..")");
end end
end end
end end
...@@ -3546,7 +3546,7 @@ function wbgen_generate_eic() ...@@ -3546,7 +3546,7 @@ function wbgen_generate_eic()
if(periph.irqcount==0)then return;end if(periph.irqcount==0)then return;end
local t=0; local t=0;
local s={}; local s={};
local o={["__type"]=TYPE_REG; local n={["__type"]=TYPE_REG;
["__blockindex"]=1e6; ["__blockindex"]=1e6;
["align"]=8; ["align"]=8;
["name"]="Interrupt disable register"; ["name"]="Interrupt disable register";
...@@ -3562,7 +3562,7 @@ signal(BIT,0,"eic_idr_write_int");}; ...@@ -3562,7 +3562,7 @@ signal(BIT,0,"eic_idr_write_int");};
["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));}; ["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true; ["no_std_regbank"]=true;
}; };
local a={["__type"]=TYPE_REG; local o={["__type"]=TYPE_REG;
["__blockindex"]=1000001; ["__blockindex"]=1000001;
["align"]=1; ["align"]=1;
["name"]="Interrupt enable register"; ["name"]="Interrupt enable register";
...@@ -3578,7 +3578,7 @@ signal(BIT,0,"eic_ier_write_int");}; ...@@ -3578,7 +3578,7 @@ signal(BIT,0,"eic_ier_write_int");};
["extra_code"]={va(vi("eic_ier_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));}; ["extra_code"]={va(vi("eic_ier_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true; ["no_std_regbank"]=true;
}; };
local n={["__type"]=TYPE_REG; local a={["__type"]=TYPE_REG;
["__blockindex"]=1000002; ["__blockindex"]=1000002;
["align"]=1; ["align"]=1;
["name"]="Interrupt status register"; ["name"]="Interrupt status register";
...@@ -3614,7 +3614,7 @@ e.index=t; ...@@ -3614,7 +3614,7 @@ e.index=t;
t=t+1; t=t+1;
table.insert(s,{["index"]=e.index;["trigger"]=e.trigger;}); table.insert(s,{["index"]=e.index;["trigger"]=e.trigger;});
fix_prefix(e); fix_prefix(e);
local s={ local t={
["__blockindex"]=e.index; ["__blockindex"]=e.index;
["__type"]=TYPE_FIELD; ["__type"]=TYPE_FIELD;
["type"]=BIT; ["type"]=BIT;
...@@ -3625,7 +3625,7 @@ local s={ ...@@ -3625,7 +3625,7 @@ local s={
["access_bus"]=READ_WRITE; ["access_bus"]=READ_WRITE;
["access_dev"]=READ_WRITE; ["access_dev"]=READ_WRITE;
}; };
local t={ local s={
["__blockindex"]=e.index; ["__blockindex"]=e.index;
["__type"]=TYPE_FIELD; ["__type"]=TYPE_FIELD;
["type"]=BIT; ["type"]=BIT;
...@@ -3667,18 +3667,18 @@ end ...@@ -3667,18 +3667,18 @@ end
if(e.mask_line==true)then if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");}); table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end end
table.insert(o,h); table.insert(n,h);
table.insert(n,s);
table.insert(i,r);
table.insert(a,t); table.insert(a,t);
table.insert(i,r);
table.insert(o,s);
end); end);
add_global_signals({ add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int"); signal(SLV,periph.irqcount,"irq_inputs_vector_int");
}); });
table.insert(periph,n);
table.insert(periph,o); table.insert(periph,o);
table.insert(periph,a);
table.insert(periph,i); table.insert(periph,i);
table.insert(periph,n); table.insert(periph,a);
local e={vgm("g_num_interrupts",periph.irqcount); local e={vgm("g_num_interrupts",periph.irqcount);
vpm("clk_i","clk_sys_i"); vpm("clk_i","clk_sys_i");
vpm("rst_n_i","rst_n_i"); vpm("rst_n_i","rst_n_i");
...@@ -3694,12 +3694,12 @@ vpm("reg_isr_i","eic_isr_clear_int"); ...@@ -3694,12 +3694,12 @@ vpm("reg_isr_i","eic_isr_clear_int");
vpm("reg_isr_wr_stb_i","eic_isr_write_int"); vpm("reg_isr_wr_stb_i","eic_isr_write_int");
vpm("wb_irq_o","wb_int_o"); vpm("wb_irq_o","wb_int_o");
}; };
local t; local a;
for o,a in ipairs(s)do for o,t in ipairs(s)do
table_join(e,{vgm(string.format("g_irq%02x_mode",a.index),a.trigger)}); table_join(e,{vgm(string.format("g_irq%02x_mode",t.index),t.trigger)});
t=o; a=o;
end end
for t=t,31 do for t=a,31 do
table_join(e,{vgm(string.format("g_irq%02x_mode",t),0)}); table_join(e,{vgm(string.format("g_irq%02x_mode",t),0)});
end end
local t={vinstance("eic_irq_controller_inst","wbgen2_eic",e);}; local t={vinstance("eic_irq_controller_inst","wbgen2_eic",e);};
...@@ -3875,20 +3875,20 @@ local s={ ...@@ -3875,20 +3875,20 @@ local s={
["hdl_prefix"]=e.hdl_prefix.."_CSR"; ["hdl_prefix"]=e.hdl_prefix.."_CSR";
["no_std_regbank"]=true; ["no_std_regbank"]=true;
}; };
function gen_fifo_csr_field(r,n,a,d,h,o,t,i) function gen_fifo_csr_field(d,n,a,t,h,o,r,i)
if(e.flags_bus==nil)then if(e.flags_bus==nil)then
return; return;
end end
if inset(r,e.flags_bus)then if inset(d,e.flags_bus)then
local t={ local t={
["__type"]=TYPE_FIELD; ["__type"]=TYPE_FIELD;
["name"]=a; ["name"]=a;
["description"]=d; ["description"]=t;
["access_bus"]=READ_ONLY; ["access_bus"]=READ_ONLY;
["access_dev"]=WRITE_ONLY; ["access_dev"]=WRITE_ONLY;
["type"]=o; ["type"]=o;
["size"]=h; ["size"]=h;
["offset"]=t; ["offset"]=r;
["c_prefix"]=n; ["c_prefix"]=n;
["hdl_prefix"]=n; ["hdl_prefix"]=n;
["signals"]={}; ["signals"]={};
...@@ -4069,8 +4069,13 @@ local e=math.max(1,address_bus_width); ...@@ -4069,8 +4069,13 @@ local e=math.max(1,address_bus_width);
local e={signal(SLV,MAX_ACK_LENGTH,"ack_sreg"), local e={signal(SLV,MAX_ACK_LENGTH,"ack_sreg"),
signal(SLV,DATA_BUS_WIDTH,"rddata_reg"), signal(SLV,DATA_BUS_WIDTH,"rddata_reg"),
signal(SLV,DATA_BUS_WIDTH,"wrdata_reg"), signal(SLV,DATA_BUS_WIDTH,"wrdata_reg"),
signal(SLV,DATA_BUS_WIDTH/8,"bwsel_reg"),
signal(SLV,e,"rwaddr_reg"), signal(SLV,e,"rwaddr_reg"),
signal(BIT,0,"ack_in_progress") signal(BIT,0,"ack_in_progress"),
signal(BIT,0,"wr_int"),
signal(BIT,0,"rd_int"),
signal(SLV,DATA_BUS_WIDTH,"allones"),
signal(SLV,DATA_BUS_WIDTH,"allzeros")
}; };
add_global_signals(e); add_global_signals(e);
end end
...@@ -4100,12 +4105,12 @@ table_join(i,e.ackgen_code_pre); ...@@ -4100,12 +4105,12 @@ table_join(i,e.ackgen_code_pre);
end); end);
local e={}; local e={};
foreach_reg({TYPE_REG},function(t) foreach_reg({TYPE_REG},function(t)
local n=find_max(t,"acklen"); local i=find_max(t,"acklen");
local a={}; local a={};
local o={}; local o={};
foreach_subfield(t,function(e,t)table_join(o,e.write_code);end); foreach_subfield(t,function(e,t)table_join(o,e.write_code);end);
foreach_subfield(t,function(e,t)table_join(a,e.read_code);end); foreach_subfield(t,function(e,t)table_join(a,e.read_code);end);
local i=fill_unused_bits("rddata_reg",t); local n=fill_unused_bits("rddata_reg",t);
table_join(o,t.write_code); table_join(o,t.write_code);
table_join(a,t.read_code); table_join(a,t.read_code);
local a={ local a={
...@@ -4113,10 +4118,10 @@ vif(vequal("wb_we_i",1),{ ...@@ -4113,10 +4118,10 @@ vif(vequal("wb_we_i",1),{
o, o,
}); });
a, a,
i n
}; };
if(not(t.dont_emit_ack_code==true))then if(not(t.dont_emit_ack_code==true))then
table_join(a,{va(vi("ack_sreg",math.max(n-1,0)),1);}); table_join(a,{va(vi("ack_sreg",math.max(i-1,0)),1);});
table_join(a,{va("ack_in_progress",1);}); table_join(a,{va("ack_in_progress",1);});
end end
if(regbank_address_bits>0)then if(regbank_address_bits>0)then
...@@ -4137,13 +4142,13 @@ local t={}; ...@@ -4137,13 +4142,13 @@ local t={};
if(periph.fifocount+periph.regcount>0)then if(periph.fifocount+periph.regcount>0)then
t={vcase(0,e);}; t={vcase(0,e);};
end end
foreach_reg({TYPE_RAM},function(a) foreach_reg({TYPE_RAM},function(e)
local e=csel(options.register_data_output,1,0); local a=csel(options.register_data_output,1,0);
table_join(t,{vcase(a.select_bits,{ table_join(t,{vcase(e.select_bits,{
vif(vequal("rd_int",1),{ vif(vequal("rd_int",1),{
va(vi("ack_sreg",0),1); va(vi("ack_sreg",0),1);
},{ },{
va(vi("ack_sreg",e),1); va(vi("ack_sreg",a),1);
}); });
va("ack_in_progress",1); va("ack_in_progress",1);
});}); });});
...@@ -4183,6 +4188,15 @@ e ...@@ -4183,6 +4188,15 @@ e
}); });
}; };
if(periph.ramcount>0)then if(periph.ramcount>0)then
local t={
vcomment("Some internal signals assignments used by RAMs.");
va("bwsel_reg","wb_sel_i");
va("rd_int",vand("wb_cyc_i",vand("wb_stb_i",vnot("wb_we_i"))));
va("wr_int",vand("wb_cyc_i",vand("wb_stb_i","wb_we_i")));
va("allones",vothers(1));
va("allzeros",vothers(0));
};
table_join(e,t);
if(not options.register_data_output)then if(not options.register_data_output)then
local t={"rddata_reg","rwaddr_reg"}; local t={"rddata_reg","rwaddr_reg"};
local a={}; local a={};
......
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