urv_fetch.v: add g_with_hw_debug parameter to optimize code

dada75d4 · Tristan Gingold · 8d8f369a · dada75d4 · dada75d4
Commit dada75d4 authored Oct 11, 2022 by Tristan Gingold
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Showing with 8 additions and 3 deletions

urv_cpu.v rtl/urv_cpu.v +4 -1

urv_fetch.v rtl/urv_fetch.v +4 -2

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--- a/rtl/urv_cpu.v
+++ b/rtl/urv_cpu.v
@@ -172,6 +172,7 @@ module urv_cpu
   urv_fetch
    #(
+      .g_with_hw_debug(g_with_hw_debug),
      .g_with_compressed_insns(g_with_compressed_insns)
      )
   fetch
@@ -267,7 +268,9 @@ module urv_cpu
   // Register File (RF)
   urv_regfile
-     #(.g_with_ecc(g_with_ecc))
+     #(
+       .g_with_ecc(g_with_ecc)
+       )
   regfile
     (
      .clk_i(clk_i),

--- a/rtl/urv_fetch.v
+++ b/rtl/urv_fetch.v
@@ -59,6 +59,7 @@ module urv_fetch
 );
   parameter g_with_compressed_insns = 0;
+   parameter g_with_hw_debug = 0;
   reg [31:0] pc;
   reg 	      rst_d;
@@ -120,7 +121,8 @@ module urv_fetch
 	       f_pc_o <= pc;
               pc <= pc_next;
-               if(!dbg_mode
+               if(g_with_hw_debug
+                  && !dbg_mode
                  && (dbg_force_i || x_dbg_toggle_i || pipeline_cnt != 0))
                 begin
                    //  Enter or entering in debug mode
@@ -137,7 +139,7 @@ module urv_fetch
                    else
                      pipeline_cnt <= pipeline_cnt + 1'b1;
                 end
-               else if(dbg_mode)
+               else if(g_with_hw_debug && dbg_mode)
                 begin
                    //  In debug mode
                    if (x_dbg_toggle_i)