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urv-core
Commit 48681306 authored by Mattia Rizzi's avatar Mattia Rizzi
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modifications for hydra 

Signed-off-by: Mattia Rizzi's avatarMattia Rizzi <mattia.rizzi@cern.ch>
parent 193f15db
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Showing with 90 additions and 61 deletions
rtl/urv_cpu.v
View file @ 48681306
...@@ -32,8 +32,8 @@ module urv_cpu ...@@ -32,8 +32,8 @@ module urv_cpu
#( #(
parameter g_timer_frequency = 1000, parameter g_timer_frequency = 1000,
parameter g_clock_frequency = 100000000, parameter g_clock_frequency = 100000000,
parameter g_with_hw_div = 1, parameter g_with_hw_div = 0,
parameter g_with_hw_mulh = 1, parameter g_with_hw_mulh = 0,
parameter g_with_hw_debug = 0, parameter g_with_hw_debug = 0,
parameter g_with_compressed_insns = 0, parameter g_with_compressed_insns = 0,
parameter g_debug_breakpoints = 6 parameter g_debug_breakpoints = 6
...@@ -60,7 +60,7 @@ module urv_cpu ...@@ -60,7 +60,7 @@ module urv_cpu
output dm_store_o, output dm_store_o,
output dm_load_o, output dm_load_o,
input dm_load_done_i, input dm_load_done_i,
input dm_store_done_i, input dm_store_done_i
// Debug I/F // Debug I/F
// Debug mode is entered either when dbg_force_i is set, or when the ebreak // Debug mode is entered either when dbg_force_i is set, or when the ebreak
...@@ -71,16 +71,8 @@ module urv_cpu ...@@ -71,16 +71,8 @@ module urv_cpu
// In debug mode, instructions are executed from dbg_insn_i. // In debug mode, instructions are executed from dbg_insn_i.
// As instructions are always fetched, they must be always valid. Use // As instructions are always fetched, they must be always valid. Use
// a nop (0x13) if nothing should be executed. // a nop (0x13) if nothing should be executed.
input dbg_force_i,
output dbg_enabled_o, ) /* synthesis syn_radhardlevel="tmr" */;
input [31:0] dbg_insn_i,
input dbg_insn_set_i,
output dbg_insn_ready_o,
input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o
);
// pipeline control // pipeline control
...@@ -179,7 +171,7 @@ module urv_cpu ...@@ -179,7 +171,7 @@ module urv_cpu
.x_pc_bra_i(x2f_pc_bra), .x_pc_bra_i(x2f_pc_bra),
.x_bra_i(x2f_bra), .x_bra_i(x2f_bra),
.dbg_force_i(dbg_force_i), .dbg_force_i(0),
.dbg_enabled_o(dbg_enabled_o), .dbg_enabled_o(dbg_enabled_o),
.dbg_insn_i(dbg_insn_i), .dbg_insn_i(dbg_insn_i),
.dbg_insn_set_i(dbg_insn_set_i), .dbg_insn_set_i(dbg_insn_set_i),
...@@ -420,7 +412,7 @@ module urv_cpu ...@@ -420,7 +412,7 @@ module urv_cpu
// pipeline control // pipeline control
assign f_stall = x_stall_req || w_stall_req || d_stall_req; assign f_stall = x_stall_req || w_stall_req || d_stall_req;
assign d_stall = x_stall_req || w_stall_req; assign d_stall = x_stall_req || w_stall_req;
assign x_stall = x_stall_req || w_stall_req; assign x_stall = x_stall_req || w_stall_req || (!im_valid_i & x2f_bra);
assign x_kill = x2f_bra || x2f_bra_d0 || x2f_bra_d1; assign x_kill = x2f_bra || x2f_bra_d0 || x2f_bra_d1;
assign d_kill = x2f_bra || x2f_bra_d0; assign d_kill = x2f_bra || x2f_bra_d0;
......
rtl/urv_csr.v
View file @ 48681306
...@@ -35,8 +35,9 @@ module urv_csr ...@@ -35,8 +35,9 @@ module urv_csr
input x_stall_i, input x_stall_i,
input x_kill_i, input x_kill_i,
input d_is_csr_i, input d_is_csr_i,
input d_valid_i,
input [2:0] d_fun_i, input [2:0] d_fun_i,
input [4:0] d_csr_imm_i, input [4:0] d_csr_imm_i,
input [11:0] d_csr_sel_i, input [11:0] d_csr_sel_i,
...@@ -143,7 +144,7 @@ module urv_csr ...@@ -143,7 +144,7 @@ module urv_csr
if (dbg_mbx_write_i && g_with_hw_debug) if (dbg_mbx_write_i && g_with_hw_debug)
mbx_data <= dbg_mbx_data_i; mbx_data <= dbg_mbx_data_i;
if(!x_stall_i && !x_kill_i && d_is_csr_i) if(!x_stall_i && !x_kill_i && d_valid_i && d_is_csr_i)
case (d_csr_sel_i) case (d_csr_sel_i)
`CSR_ID_MSCRATCH: `CSR_ID_MSCRATCH:
csr_mscratch <= csr_out; csr_mscratch <= csr_out;
......
rtl/urv_debug.v
View file @ 48681306
...@@ -40,7 +40,7 @@ module urv_debug ...@@ -40,7 +40,7 @@ module urv_debug
input dm_ready_i, input dm_ready_i,
output [4:0] rf_index_o, output [4:0] rf_index_o,
input [31:0] rf_data_r_i input [31:0] rf_data_r_i,
output [31:0] rf_data_w_o, output [31:0] rf_data_w_o,
output rf_write_o, output rf_write_o,
......
rtl/urv_exceptions.v
View file @ 48681306
...@@ -90,44 +90,47 @@ module urv_exceptions ...@@ -90,44 +90,47 @@ module urv_exceptions
begin begin
csr_mcause_code <= 0; csr_mcause_code <= 0;
csr_mcause_interrupt <= 0; csr_mcause_interrupt <= 0;
csr_mepc <= 0; csr_mepc <= 0;
csr_mie <= 0; csr_mie <= 0;
csr_status_mie <= 0; csr_status_mie <= 0;
csr_status_mpie <= 0; csr_status_mpie <= 0;
end end
else else
begin begin : blk
if (x_exception_i) reg new_status_mie;
begin
csr_mepc <= x_exception_pc_i; new_status_mie = csr_status_mie;
csr_mcause_code <= x_exception_cause_i;
csr_mcause_interrupt <= x_interrupt_i;
// Mask interrupts during exceptions
csr_status_mpie <= csr_status_mie;
csr_status_mie <= 0;
end
if (!x_stall_i && !x_kill_i) if (!x_stall_i && !x_kill_i)
begin begin
if (d_is_csr_i) if (d_is_csr_i)
case (d_csr_sel_i) case (d_csr_sel_i)
`CSR_ID_MSTATUS: `CSR_ID_MSTATUS:
csr_status_mie <= x_csr_write_value_i[3]; new_status_mie = x_csr_write_value_i[3];
`CSR_ID_MEPC: `CSR_ID_MEPC:
csr_mepc <= x_csr_write_value_i; csr_mepc <= x_csr_write_value_i;
`CSR_ID_MIE: `CSR_ID_MIE:
begin begin
csr_mie[`EXCEPT_TIMER] <= csr_mie[`EXCEPT_TIMER] <=
x_csr_write_value_i[`EXCEPT_TIMER]; x_csr_write_value_i[`EXCEPT_TIMER];
csr_mie[`EXCEPT_IRQ] <= csr_mie[`EXCEPT_IRQ] <=
x_csr_write_value_i[`EXCEPT_IRQ]; x_csr_write_value_i[`EXCEPT_IRQ];
end end
endcase endcase
if (d_is_mret_i) if (d_is_mret_i)
csr_status_mie <= csr_status_mpie; new_status_mie = csr_status_mpie;
end end
if (x_exception_i)
begin
csr_mepc <= x_exception_pc_i;
csr_mcause_code <= x_exception_cause_i;
csr_mcause_interrupt <= x_interrupt_i;
// Mask interrupts during exceptions
csr_status_mpie <= new_status_mie;
new_status_mie = 0;
end
csr_status_mie <= new_status_mie;
end end
assign x_exception_pc_o = csr_mepc; assign x_exception_pc_o = csr_mepc;
......
rtl/urv_exec.v
View file @ 48681306
...@@ -173,6 +173,7 @@ module urv_exec ...@@ -173,6 +173,7 @@ module urv_exec
.x_kill_i(x_kill_i), .x_kill_i(x_kill_i),
.d_is_csr_i(d_is_csr_i), .d_is_csr_i(d_is_csr_i),
.d_valid_i(d_valid_i),
.d_fun_i(d_fun_i), .d_fun_i(d_fun_i),
.d_csr_imm_i(d_csr_imm_i), .d_csr_imm_i(d_csr_imm_i),
.d_csr_sel_i (d_csr_sel_i), .d_csr_sel_i (d_csr_sel_i),
...@@ -311,7 +312,7 @@ module urv_exec ...@@ -311,7 +312,7 @@ module urv_exec
wire divider_stall_req; wire divider_stall_req;
wire multiply_stall_req; wire multiply_stall_req;
/*
urv_multiply urv_multiply
#( #(
.g_with_hw_mulh( g_with_hw_mulh ) .g_with_hw_mulh( g_with_hw_mulh )
...@@ -330,10 +331,12 @@ module urv_exec ...@@ -330,10 +331,12 @@ module urv_exec
.d_is_multiply_i(d_is_multiply_i), .d_is_multiply_i(d_is_multiply_i),
.w_rd_o (w_rd_multiply_o), .w_rd_o (w_rd_multiply_o),
.x_rd_o (rd_mulh) .x_rd_o (rd_mulh)
); );*/
assign w_rd_multiply_o = 0;
wire [31:0] rd_divide; wire [31:0] rd_divide;
/*
generate generate
if(g_with_hw_div) if(g_with_hw_div)
urv_divide divider urv_divide divider
...@@ -357,7 +360,8 @@ module urv_exec ...@@ -357,7 +360,8 @@ module urv_exec
else else
assign divider_stall_req = 1'b0; assign divider_stall_req = 1'b0;
endgenerate endgenerate
*/
assign divider_stall_req = 1'b0;
always@* always@*
case (d_rd_source_i) case (d_rd_source_i)
`RD_SOURCE_ALU: rd_value <= alu_result; `RD_SOURCE_ALU: rd_value <= alu_result;
......
rtl/urv_fetch.v
View file @ 48681306
...@@ -54,7 +54,7 @@ module urv_fetch ...@@ -54,7 +54,7 @@ module urv_fetch
input dbg_insn_set_i, input dbg_insn_set_i,
output dbg_insn_ready_o, output dbg_insn_ready_o,
input x_dbg_toggle_i input x_dbg_toggle_i
); ) /* synthesis syn_radhardlevel="tmr" */;
parameter g_with_compressed_insns = 0; parameter g_with_compressed_insns = 0;
...@@ -66,7 +66,9 @@ module urv_fetch ...@@ -66,7 +66,9 @@ module urv_fetch
reg [2:0] pipeline_cnt; reg [2:0] pipeline_cnt;
always@* always@*
if( x_bra_i ) if (!im_valid_i)
pc_next <= pc;
else if( x_bra_i )
pc_next <= x_pc_bra_i; pc_next <= x_pc_bra_i;
else if (!rst_d || f_stall_i || !im_valid_i else if (!rst_d || f_stall_i || !im_valid_i
|| dbg_mode || dbg_force_i || pipeline_cnt != 0) || dbg_mode || dbg_force_i || pipeline_cnt != 0)
......
rtl/urv_regfile.v
View file @ 48681306
...@@ -89,10 +89,12 @@ module urv_regfile ...@@ -89,10 +89,12 @@ module urv_regfile
); );
reg [4:0] w_rd;
reg [31:0] w_rd_value;
wire [31:0] rs1_regfile; wire [31:0] rs1_regfile;
wire [31:0] rs2_regfile; wire [31:0] rs2_regfile;
wire write = (w_rd_store_i && (w_rd_i != 0)); wire write = rst_i || (w_rd_store_i && (w_rd_i != 0));
reg [31:0] ra,sp;
urv_regmem bank0 urv_regmem bank0
( (
...@@ -102,8 +104,8 @@ module urv_regfile ...@@ -102,8 +104,8 @@ module urv_regfile
.a1_i(rf_rs1_i), .a1_i(rf_rs1_i),
.q1_o(rs1_regfile), .q1_o(rs1_regfile),
.a2_i(w_rd_i), .a2_i(w_rd),
.d2_i(w_rd_value_i), .d2_i(w_rd_value),
.we2_i (write)); .we2_i (write));
...@@ -115,8 +117,8 @@ module urv_regfile ...@@ -115,8 +117,8 @@ module urv_regfile
.a1_i(rf_rs2_i), .a1_i(rf_rs2_i),
.q1_o(rs2_regfile), .q1_o(rs2_regfile),
.a2_i (w_rd_i), .a2_i (w_rd),
.d2_i (w_rd_value_i), .d2_i (w_rd_value),
.we2_i (write) .we2_i (write)
); );
...@@ -162,4 +164,29 @@ module urv_regfile ...@@ -162,4 +164,29 @@ module urv_regfile
endcase // case ( {rs2_bypass_x, rs2_bypass_w } ) endcase // case ( {rs2_bypass_x, rs2_bypass_w } )
end // always@ * end // always@ *
endmodule // urv_regfile
always@*
begin
if (rst_i)
begin
w_rd <= 0;
w_rd_value <= 0;
end
else
begin
w_rd <= w_rd_i;
w_rd_value <= w_rd_value_i;
end
end
always@(posedge clk_i)
if(write && w_rd_i == 1)
ra <= w_rd_value;
always@(posedge clk_i)
if(write && w_rd_i == 2)
sp <= w_rd_value;
endmodule // urv_regfile
\ No newline at end of file
rtl/urv_timer.v
View file @ 48681306
...@@ -40,7 +40,7 @@ module urv_timer ...@@ -40,7 +40,7 @@ module urv_timer
); );
parameter g_timer_frequency = 1000; parameter g_timer_frequency = 1000;
parameter g_clock_frequency = 62500000; parameter g_clock_frequency = 50000000;
localparam g_prescaler = (g_clock_frequency / g_timer_frequency ) - 1; localparam g_prescaler = (g_clock_frequency / g_timer_frequency ) - 1;
......
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