update licenses

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

update licenses
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
fc56f159 · Federico Vaga · d370141f · fc56f159 · fc56f159 · fc56f159
Commit fc56f159 authored Nov 25, 2020 by Federico Vaga
53 changed files
--- a/.gitignore
+++ b/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 *.o
 *.ko
 *.mod.c

--- a/.gitmodules
+++ b/.gitmodules
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 [submodule "hdl/ip_cores/wr-cores"]
 	path = hdl/ip_cores/wr-cores
 	url = https://ohwr.org/project/wr-cores.git

--- a/LICENSES/CERN-OHL-W-2.0+.txt
+++ b/LICENSES/CERN-OHL-W-2.0+.txt
+CERN-OHL-W-2.0.txt
\ No newline at end of file
--- a/LICENSES/CERN-OHL-W-2.0.txt
+++ b/LICENSES/CERN-OHL-W-2.0.txt
--- a/Manifest.py
+++ b/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 modules = { "local" : [ "hdl/rtl" ] }
 if action == "synthesis":

--- a/README.rst
+++ b/README.rst
+..
+  SPDX-FileCopyrightText: 2020 CERN (home.cern)
+  SPDX-License-Identifier: CC0-1.0
 ==============================
 Simple PCIe FMC Carrier - SPEC
 ==============================

--- a/distribution/.gitignore
+++ b/distribution/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 build
 rpmbuild
 sources
--- a/distribution/Makefile
+++ b/distribution/Makefile
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 TOP_DIR ?= $(shell pwd)/../
 HDL_DIR ?= $(TOP_DIR)/hdl

--- a/distribution/dkms.conf
+++ b/distribution/dkms.conf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 PACKAGE_NAME="@PKGNAME@"
 PACKAGE_VERSION="@PKGVER@"
 CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"

--- a/doc/.gitignore
+++ b/doc/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 _build/
--- a/doc/Makefile
+++ b/doc/Makefile
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # Minimal makefile for Sphinx documentation
 #

--- a/doc/conf.py
+++ b/doc/conf.py
+# SPDX-FileCopyrightText: 2020
+#
+# SPDX-License-Identifier: CC0-1.0
 # -*- coding: utf-8 -*-
 #
 # Configuration file for the Sphinx documentation builder.

--- a/hdl/rtl/.gitignore
+++ b/hdl/rtl/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 sourceid_spec_base_pkg.vhd
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 files = [
    "spec_base_regs.vhd",
    "spec_base_wr.vhd",

--- a/hdl/rtl/spec_base_regs.cheby
+++ b/hdl/rtl/spec_base_regs.cheby
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
 memory-map:
  name: spec_base_regs
  bus: wb-32-be

--- a/hdl/rtl/spec_base_regs.vhd
+++ b/hdl/rtl/spec_base_regs.vhd
+-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
 -- Do not edit; this file was generated by Cheby using these options:
 --  --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby

--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
 --------------------------------------------------------------------------------
+-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+--
 -- CERN BE-CO-HT
 -- SPEC
 -- https://ohwr.org/projects/spec
@@ -9,18 +13,6 @@
 -- description: SPEC carrier base.
 --
 --------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;

--- a/hdl/syn/common/Manifest.py
+++ b/hdl/syn/common/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 files = ["spec_base_common.ucf"]
 ucf_dict = {'wr':      "spec_base_wr.ucf",

--- a/hdl/syn/common/spec_base_common.ucf
+++ b/hdl/syn/common/spec_base_common.ucf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 #===============================================================================
 # IO Constraints
 #===============================================================================

--- a/hdl/syn/common/spec_base_ddr3.ucf
+++ b/hdl/syn/common/spec_base_ddr3.ucf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 ## DDR-3
 NET "ddr_rzq_b"     LOC = K7;
 NET "ddr_we_n_o"    LOC = H2;

--- a/hdl/syn/common/spec_base_onewire.ucf
+++ b/hdl/syn/common/spec_base_onewire.ucf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 ###########################################################################
 ## Onewire interface -> thermometer
 ###########################################################################

--- a/hdl/syn/common/spec_base_spi.ucf
+++ b/hdl/syn/common/spec_base_spi.ucf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 ###########################################################################
 ## Flash memory SPI interface
 ###########################################################################

--- a/hdl/syn/common/spec_base_wr.ucf
+++ b/hdl/syn/common/spec_base_wr.ucf
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 #===============================================================================
 # IO Location Constraints
 #===============================================================================

--- a/hdl/syn/golden-100T/.gitignore
+++ b/hdl/syn/golden-100T/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 *
 !.gitignore
 !Manifest.py

--- a/hdl/syn/golden-100T/Manifest.py
+++ b/hdl/syn/golden-100T/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 target = "xilinx"
 action = "synthesis"
 board  = "spec"

--- a/hdl/syn/golden-100T/syn_extra_steps.tcl
+++ b/hdl/syn/golden-100T/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]

--- a/hdl/syn/golden-150T/.gitignore
+++ b/hdl/syn/golden-150T/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 *
 !.gitignore
 !Manifest.py

--- a/hdl/syn/golden-150T/Manifest.py
+++ b/hdl/syn/golden-150T/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 target = "xilinx"
 action = "synthesis"
 board  = "spec"

--- a/hdl/syn/golden-150T/syn_extra_steps.tcl
+++ b/hdl/syn/golden-150T/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]

--- a/hdl/syn/golden-45T/.gitignore
+++ b/hdl/syn/golden-45T/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 *
 !.gitignore
 !Manifest.py

--- a/hdl/syn/golden-45T/Manifest.py
+++ b/hdl/syn/golden-45T/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 target = "xilinx"
 action = "synthesis"
 board  = "spec"

--- a/hdl/syn/golden-45T/syn_extra_steps.tcl
+++ b/hdl/syn/golden-45T/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]

--- a/hdl/syn/wr_example/.gitignore
+++ b/hdl/syn/wr_example/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 *
 !.gitignore
 !Manifest.py

--- a/hdl/syn/wr_example/Manifest.py
+++ b/hdl/syn/wr_example/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 target = "xilinx"
 action = "synthesis"
 board  = "spec"

--- a/hdl/syn/wr_example/syn_extra_steps.tcl
+++ b/hdl/syn/wr_example/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]

--- a/hdl/testbench/golden/.gitignore
+++ b/hdl/testbench/golden/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 Makefile
 work/
 transcript

--- a/hdl/testbench/golden/Manifest.py
+++ b/hdl/testbench/golden/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 board      = "spec"
 sim_tool   = "modelsim"
 sim_top    = "main"

--- a/hdl/testbench/golden/main.sv
+++ b/hdl/testbench/golden/main.sv
+// SPDX-FileCopyrightText: 2020 CERN (home.cern)
+//
+// SPDX-License-Identifier: CC0-1.0
 `timescale 1ns/1ps
 `include "gn4124_bfm.svh"

--- a/hdl/testbench/golden/run.do
+++ b/hdl/testbench/golden/run.do
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -voptargs="+acc" -sv_seed random
 set StdArithNoWarnings 1

--- a/hdl/testbench/golden/run_ci.do
+++ b/hdl/testbench/golden/run_ci.do
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -sv_seed random
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1

--- a/hdl/testbench/golden/wave.do
+++ b/hdl/testbench/golden/wave.do
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate -group {App DDR port} -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/rst_n_i

--- a/hdl/top/golden/Manifest.py
+++ b/hdl/top/golden/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # Allow the user to override fetchto using:
 #  hdlmake -p "fetchto='xxx'"
 if locals().get('fetchto', None) is None:

--- a/hdl/top/golden/spec_golden.vhd
+++ b/hdl/top/golden/spec_golden.vhd
 --------------------------------------------------------------------------------
+-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+--
 -- CERN BE-CO-HT
 -- SPEC
 -- https://ohwr.org/projects/spec
@@ -9,18 +13,6 @@
 -- description: SPEC golden design, without WR.
 --
 --------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;

--- a/hdl/top/wr_example/Manifest.py
+++ b/hdl/top/wr_example/Manifest.py
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 files = ["spec_base_wr_example.vhd"]
 modules = {'local': ["../../rtl"]}
--- a/hdl/top/wr_example/spec_base_wr_example.vhd
+++ b/hdl/top/wr_example/spec_base_wr_example.vhd
 --------------------------------------------------------------------------------
+-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+--
 -- CERN BE-CO-HT
 -- SPEC
 -- https://ohwr.org/projects/spec
@@ -9,18 +13,6 @@
 -- description: Example instantiation of SPEC base with White Rabbit.
 --
 --------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;

--- a/software/Makefile
+++ b/software/Makefile
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 -include Makefile.specific
 -include $(REPO_PARENT)/parent_common.mk

--- a/software/include/uapi/linux/spec.h
+++ b/software/include/uapi/linux/spec.h
-/*
+// Copyright (C) 2020 CERN (www.cern.ch)
- * Copyright (C) 2020 CERN (www.cern.ch)
+// SPDX-FileCopyrightText: 2020 CERN (home.cern)
- * Author: Federico Vaga <federico.vaga@cern.ch>
+//
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Author: Federico Vaga <federico.vaga@cern.ch>
 #ifndef __LINUX_UAPI_SPEC_H
 #define __LINUX_UAPI_SPEC_H

--- a/software/kernel/.clang-format
+++ b/software/kernel/.clang-format
+# SPDX-FileCopyrightText: Linux
+#
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
 # clang-format configuration file. Intended for clang-format >= 4.

--- a/software/kernel/.gitignore
+++ b/software/kernel/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 spec-core-fpga.h
\ No newline at end of file
--- a/software/kernel/Kbuild
+++ b/software/kernel/Kbuild
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 # add versions of supermodule. It is useful when spec is included as sub-module
 # of a bigger project that we want to track
 ifdef CONFIG_SUPER_REPO

--- a/software/kernel/Makefile
+++ b/software/kernel/Makefile
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 -include Makefile.specific
 -include $(REPO_PARENT)/parent_common.mk

--- a/software/tools/.gitignore
+++ b/software/tools/.gitignore
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
 spec-firmware-version
--- a/software/tools/spec_dma_throughput.py
+++ b/software/tools/spec_dma_throughput.py
 #!/usr/bin/python3
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
 import os
 import re
 import argparse