- 14 Dec, 2017 1 commit
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Michael Reese authored
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- 15 Aug, 2017 1 commit
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Michael Reese authored
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- 14 Aug, 2017 1 commit
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Michael Reese authored
vme-wb: allow remapping of AM=0x09 address range to slot*0x01000000 by enlarging ADEM register for function 0
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- 11 Aug, 2017 1 commit
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Michael Reese authored
the VME-WB bridge is initially in a "normal" mode. In this mode, etherbone access works as ususal. The VME-WB bridge has now tow additional registers that are accessible using a AM=0x39 access. These registers have 0x400*slot as base address: register 0x4: write-only, the value written here is the wishbone base address that will be mapped onto the AM=0x09 address range with base address 0x10000000*slot (this should be changed into 0x01000000, as requested by EE). register 0xc: write-only, the value written here will be ignored, but a write access switches the VME-WB bridge back into the "normal" mode. example: configure the VMW-WB bridge to give direct VME access to the TLU registers (assuming that the TLU wishbone base address (obtained with eb-ls dev/wbm0) is 0x04000100, and assuming that slot is 2) ./vme -v 0x00000804 -w 0x4000100 -a 0x39 (vme-write: value=0x04000100 addr=0x00000804 AM=0x39) (now the bridge is in direct VME-WB mapping mode => etherbone access will not work anymore) ./vme -v 0x20000000 -s 0x04 -w 0xffffffff -a 0x09 (vme-write: value=0x3 addr=0x20000000 offset=0x04 AM=0x09) register CLR (clear) ./vme -v 0x20000000 -s 0x58 -w 0x3 -a 0x09 (vme-write: value=0x3 addr=0x20000000 offset=0x58 AM=0x09) register CH_SEL (channel select) ./vme -v 0x20000000 -s 0x10 -w 0xffffffff -a 0x09 (vme-write: value=0x3 addr=0x20000000 offset=0x10 AM=0x09) register ACT_SET (activate trigger) ./vme -v 0x20000000 -s 0x64 -a 0x09 (vme-read: addr=0x20000000 AM=0x09) register TS_CNT (fifo fill count) configure the VME-WB bridge to work in "normal" mode again (etherbone will work) ./vme -v 0x0000080c -w 0x4000100 -a 0x39
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- 09 Aug, 2017 1 commit
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Michael Reese authored
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- 09 Feb, 2017 1 commit
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Cesar Prados authored
These changes require also a driver update because the correct AM values have to be written into the ADER registers.
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- 01 Aug, 2016 1 commit
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Cesar Prados authored
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- 28 Jul, 2016 1 commit
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Cesar Prados authored
the submodule is hosted in CERN repo and as long as I could see people without CERN account are having problems to check it out.
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- 27 Jul, 2016 1 commit
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Cesar Prados authored
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- 26 Apr, 2016 2 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- 22 Apr, 2016 1 commit
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Wesley W. Terpstra authored
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- 18 Jul, 2014 2 commits
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Cesar Prados authored
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Cesar Prados authored
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- 03 Apr, 2014 2 commits
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Cesar Prados authored
in comparisons
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Cesar Prados authored
module VME_init
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- 02 Apr, 2014 4 commits
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Cesar Prados authored
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Cesar Prados authored
- compatibility with Wishbone and the VIC interrupt controller - possibility of losing an edge-triggered IRQ and hanging interrupts when different cores trigger interrupts very close to each other. The modified interrupter implements a retry mechanism, that is, if the IRQ line gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle is repeated on the VME bus. signoff Tomas.W.
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Cesar Prados authored
be addressed without conflicts using A24 only disable everything except A24/A32 VME_bus.vhd: reset internal address/AM register when AS is inactive (prevents two cards DTACKing same access bug) --signoff Tomas.W.
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Cesar Prados authored
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- 26 Mar, 2014 1 commit
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Wesley W. Terpstra authored
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- 25 Mar, 2014 1 commit
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Cesar Prados authored
kernel > 3.9, this module it is not compiled.
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- 20 Mar, 2014 4 commits
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Wesley W. Terpstra authored
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Cesar Prados authored
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Cesar Prados authored
The chip tundra doesn't support 8 bit data width transfer, it is emulated from wb master, who provides the select setting for each access. From now on the wb registers can be read/write only through the vme_wb
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Cesar Prados authored
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- 27 Feb, 2014 5 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- 20 Jan, 2014 1 commit
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Cesar Prados authored
generic. Now the the sdb is autogenerated.
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- 15 Jan, 2014 1 commit
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Wesley W. Terpstra authored
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- 14 Jan, 2014 3 commits
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Cesar Prados authored
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Cesar Prados authored
I had it in another repo, but now that the things are working better to start compacting the repos
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Cesar Prados authored
the VME_Wb interface has an additional register for controlling the msi interrupts. The rest of the changes in the VME bus and top file are for backwards compatibility. Now the user can synthesize for legacy interrupts or msi.
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- 16 Dec, 2013 3 commits
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Cesar Prados authored
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Cesar Prados authored
msi_interrupts: add MSI support to VME core. Now the src of an interrupt can be from another module (legacy interrupt) or from the MSI WB bus
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Cesar Prados authored
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- 10 Dec, 2013 1 commit
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Cesar Prados authored
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