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Commit d342f521 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Merge remote-tracking branch 'origin/release-2.1'

parents aabe6c84 8bd44158
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docs/conf.py
View file @ d342f521
...@@ -46,16 +46,16 @@ master_doc = 'index' ...@@ -46,16 +46,16 @@ master_doc = 'index'
# General information about the project. # General information about the project.
project = u'hdlmake' project = u'hdlmake'
copyright = u'2014, CERN' copyright = u'2013-2015, CERN'
# The version info for the project you're documenting, acts as replacement for # The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the # |version| and |release|, also used in various other places throughout the
# built documents. # built documents.
# #
# The short X.Y version. # The short X.Y version.
version = '2.0' version = '2.1'
# The full version, including alpha/beta/rc tags. # The full version, including alpha/beta/rc tags.
release = '2.0' release = '2.1'
# The language for content autogenerated by Sphinx. Refer to documentation # The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages. # for a list of supported languages.
......
docs/index.rst
View file @ d342f521
...@@ -6,8 +6,6 @@ ...@@ -6,8 +6,6 @@
Welcome to hdlmake's documentation! Welcome to hdlmake's documentation!
=================================== ===================================
.. warning:: The full project documentation is under development. Check this space as new content will be added in the coming days.
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
...@@ -95,6 +93,8 @@ Supported Tools ...@@ -95,6 +93,8 @@ Supported Tools
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| Xilinx PlanAhead | Yes | No | | Xilinx PlanAhead | Yes | No |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| Xilinx Vivado | Yes | No |
+--------------------------+-----------+------------+
| Altera Quartus | Yes | n.a. | | Altera Quartus | Yes | n.a. |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| Microsemi (Actel) Libero | Yes | n.a. | | Microsemi (Actel) Libero | Yes | n.a. |
...@@ -107,7 +107,7 @@ Supported Tools ...@@ -107,7 +107,7 @@ Supported Tools
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| Aldec Active-HDL | n.a. | Yes | | Aldec Active-HDL | n.a. | Yes |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| Icarus Verilog | n.a. | Verilog | | Icarus Verilog | n.a. | Yes |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| GHDL | n.a. | VHDL | | GHDL | n.a. | VHDL |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
...@@ -182,7 +182,7 @@ Despite the fact that ``hdlmake`` was originally designed to be used in Linux en ...@@ -182,7 +182,7 @@ Despite the fact that ``hdlmake`` was originally designed to be used in Linux en
First, install a valid Cygwin environment for your Windows machine. I order to access to the full set of features from ``hdlmake``, you must choose at least the following packages when deploying Cygwin: First, install a valid Cygwin environment for your Windows machine. I order to access to the full set of features from ``hdlmake``, you must choose at least the following packages when deploying Cygwin:
- python (choose the most updated 2.7 release) - python (choose the most up-to-date 2.7 release)
- openssh - openssh
- git-svn - git-svn
- git - git
...@@ -301,6 +301,8 @@ Each of the modules contains a single testbench file written in the appropriated ...@@ -301,6 +301,8 @@ Each of the modules contains a single testbench file written in the appropriated
While in Verilog the Manifest.py is: While in Verilog the Manifest.py is:
.. code-block:: python
files = [ files = [
"counter_tb.v", "counter_tb.v",
] ]
...@@ -376,7 +378,7 @@ The following common top specific Manifest variables describes the simulation: ...@@ -376,7 +378,7 @@ The following common top specific Manifest variables describes the simulation:
- ``action``: indicates that we are going to perform a simulation. - ``action``: indicates that we are going to perform a simulation.
- ``sim_tool``: indicates that modelsim is going to be the simulation we are going to use. - ``sim_tool``: indicates that modelsim is going to be the simulation we are going to use.
- ``top_module``: indicates the name of the top HDL entity/instance that is going to be simulated. - ``top_module``: indicates the name of the top HDL entity/instance that is going to be simulated.
- ``sim_post_cmd``: indicates a command that can be issued after the simulation process has finnished. - ``sim_post_cmd``: indicates a command that must be issued after the simulation process has finnished.
Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run ``hdlmake`` without arguments. e.g. for VHDL: Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run ``hdlmake`` without arguments. e.g. for VHDL:
...@@ -392,11 +394,11 @@ This generates a simulation Makefile that can be executed by issuing the well kn ...@@ -392,11 +394,11 @@ This generates a simulation Makefile that can be executed by issuing the well kn
user@host:~$ make user@host:~$ make
user@host:~$ vsim -do ../vsim.do -i counter_tb user@host:~$ vsim -do ../vsim.do -i counter_tb
But, because we have already defined a post simulation command into the Manifest.py, the generated Makefile allows us to combine the compilation and the test run in a single command: But, because we have already defined a post simulation command into the Manifest.py, the generated Makefile allows us to combine the compilation and the test run in a single command. In this way, the second command is not required:
.. code-block:: bash .. code-block:: bash
user@host:~$ make sim_post_cmd user@host:~$ make
If everything goes well, a graphical viewer should appear showing the simulated waveform. Note that every simulation top Manifest.py in the ``sim`` folder includes a tool specific ``sim_post_command``, so all the simulations in this example can be generated by using the same simple command sequence that has been exposed here. If everything goes well, a graphical viewer should appear showing the simulated waveform. Note that every simulation top Manifest.py in the ``sim`` folder includes a tool specific ``sim_post_command``, so all the simulations in this example can be generated by using the same simple command sequence that has been exposed here.
...@@ -471,6 +473,8 @@ Note that we have a different tool associated to each of the different supported ...@@ -471,6 +473,8 @@ Note that we have a different tool associated to each of the different supported
If we focus on the ``spec_v4_ise`` test case, we can see the following contents in the associated folder: If we focus on the ``spec_v4_ise`` test case, we can see the following contents in the associated folder:
.. code-block:: bash
user@host:~$ tree -d -L 1 counter/syn/spec_v4_ise user@host:~$ tree -d -L 1 counter/syn/spec_v4_ise
counter/syn/spec_v4_ise/ counter/syn/spec_v4_ise/
|-- verilog |-- verilog
...@@ -618,13 +622,268 @@ This will tell Hdlmake to fetch modules to the project catalog. Let's see how it ...@@ -618,13 +622,268 @@ This will tell Hdlmake to fetch modules to the project catalog. Let's see how it
And we finally get the original project we started with. And we finally get the original project we started with.
Pre and Post synthesis / simulation commands
--------------------------------------------
As we have already seen in the simulation example, ``hdlmake`` allows for the injection of optional external shell commands that
are executed just before and/or just after the selected action has been executed. By using this feature, we can automate other custom tasks
in addition to the ``hdlmake`` specific ones.
If a external command has been defined in the top Manifest, this is automatically written by ``hdlmake`` into the generated Makefile.
In this way, the external commands are automatically executed in order when a ``make`` command is issued.
**Synthesis:**
In order to add external commands to a synthesis top makefile, the following parameters must be introduced:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| syn_pre_cmd | str | Command to be executed before synthesis | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| syn_post_cmd | str | Command to be executed after synthesis | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
As a very simple example, we can introduce both extra commands in the top synthesis makefile we have previously seen:
.. code-block:: python
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
syn_pre_cmd = "echo This is executed just before the synthesis"
syn_post_cmd = "echo This is executed just after the synthesis"
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
**Simulation:**
Now, if we want to add external commands to a simulation top makefile, the following parameters must be introduced:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| sim_pre_cmd | str | Command to be executed before simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| sim_post_cmd | str | Command to be executed after simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
As a very simple example, we can introduce both extra commands in the top simulation makefile we have previously seen:
.. code-block:: python
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_pre_cmd = "echo This is executed just before the simulation"
sim_post_cmd = "echo This is executed just after the simulation"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
**Multiline commands:**
If you need to execute a more complex action from the pre/post synthesis/simulation commands, you can point to an
external shell script or program. As an alternative, you can use a multiline string in order to inject multiple
commands into the Makefile.
As a first option, multiple commands can be launched by spliting a single long string into one piece per command.
The drawback for this approach is that the original single line is reconstructed an inserted into the Makefile, so
the specific external command Makefile target include just a single entry. This is why, in the following example,
semicolons are used in order to separate the sequential commands:
.. code-block:: python
syn_pre_cmd = (
"mkdir /home/user/Workspace/test1;"
"mkdir /home/user/Workspace/test2;"
"mkdir /home/user/Workspace/test3;"
"mkdir /home/user/Workspace/test4;"
"mkdir /home/user/Workspace/test5"
)
A cleaner alternative, is using a multiline text in which line return and tabulation characters has been introduced
in order to separate in different lines each of the commans when they are written into the Makefiles. In the
following example, this approach is exemplified:
.. code-block:: python
syn_pre_cmd = (
"mkdir /home/user/Workspace/test1\n\t\t"
"mkdir /home/user/Workspace/test2\n\t\t"
"mkdir /home/user/Workspace/test3\n\t\t"
"mkdir /home/user/Workspace/test4\n\t\t"
"mkdir /home/user/Workspace/test5"
)
Custom variables and conditional execution
------------------------------------------
In order to give an extra level of flexibility when defining the files and modules that are going to be used in a
specific project, ``hdlmake`` allows for the introduction of custom variables in the top Manifest that can then be
accessed from inside all of the Manifests in the design hierarchy. This is a very handy feature when different synthesis
or simulation configurations in complex designs should be selected from the top level Manifest when running ``hdlmake``.
As a very simple example of how this mechanism can be used, suppose that we want to simulate a design that uses a module for which
two different harware descriptions are available, one in VHDL and one in Verilog (mixed language is a common feature of commercial
simulation tools and is an under-development feature for Icarus Verilog).
For this purpose, we introduce an ``if`` clause inside a children Manifest in which the ``simulate_vhdl`` boolean variable
is used to select the content of the following ``modules`` to be scanned:
.. code-block:: python
if simulate_vhdl:
print("We are using the VHDL module")
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
else:
print("We are using the Verilog module")
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
Now, in order to define the ``simulate_vhdl`` variable value, we can use two different approachs.
The first one is to include this as a new variable in the top Manifest.py, i.e.:
.. code-block:: python
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
simulate_vhdl = False
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
But we can also define the variable value by injecting custom Python code from the command line
when ``hdlmake`` is executed:
.. code-block:: bash
hdlmake --py "simulate_vhdl = False" auto
.. note:: New custom variables are not allowed outside the TOP Manifest.py. In this way, despite the fact that all of the Pyhton code in the used Manifest.py files is executed when ``hdlmake`` is launched, not all of the Python constructions can be implemented.
.. note:: In order to allow the insertion of new custom variables in the child Manifests, you can try the ``--allow-unknown`` experimental feature. By specifiying this optional argument to the ``hdlmake`` command line, a warning message is raised when an unknown option or variable is defined in a child Manifest.py, but the variable itself is inserted and processed.
Remote synthesis with Xilinx ISE
--------------------------------
When using ISE synthesis, ``hdlmake`` allows for the implementation of a centralized synthesis machine.
For this purpose, when running ``hdlmake`` an extra remote synthesis target is created in the Makefile so that
the actual resource intensive synthesis process is executed in a remote machine instead of in the local one.
In order to do that, when a remote synthesis is performed the local machine connects to the synthesis server through
a secure TCP/IP connection by using SSL. For this purpose, the following tools need to be installed:
+-----------+--------------------------------------------+
| Machine | Communication Software |
+===========+============================================+
| Client | ISE, ssh-server, rsync, screen (optional) |
+-----------+--------------------------------------------+
| Server | ssh-client, rsync, screen (optional) |
+-----------+--------------------------------------------+
.. note:: You'll need a local ISE deployment if you want to regenerate the synthesis Makefile or the ISE project (.xise),
files that are mandatory to perform both local and remote synthesis. But, if you have a valid Makefile and ISE project, you can
launch the remote synthesis from a local machine in which the ISE toolchain is not installed.
Before running the remote synthesis Makefile targets, there are different parameters that need to defined for proper operation.
These can be defined as shell environmental variables or, alternatively, inside the Makefile itself:
+--------------------------+--------------------+--------------------------------------------+
| Environmental Variable | Makefile Variable | Description |
+==========================+====================+============================================+
| HDLMAKE_RSYNTH_USER | USER | Remote synthesis user in the host machine |
+--------------------------+--------------------+--------------------------------------------+
| HDLMAKE_RSYNTH_SERVER | SERVER | IP/Address of the remote synthesis server |
+--------------------------+--------------------+--------------------------------------------+
| HDLMAKE_RSYNTH_ISE_PATH | ISE_PATH | Path of the ISE binaries in the server |
+--------------------------+--------------------+--------------------------------------------+
In addition, an optional ``HDLMAKE_RSYNTH_USE_SCREEN`` environmental variable can be set to 1 in order to use ``screen``
when the remote connection is stablished. If this variable is not defined or set to other value,
a standard shell connection is used (by using ``screen``, the remote synthesis feedback messages are smoothly printed).
As an example, in order to launch a remote synthesis by using the ``screen`` interface to connect with the user "javi",
available inside the 64 bit Linux machine placed at address 192.168.0.13 in the local network which features
a Xilinx ISE deployment in the default installation folder, we should issue:
.. code-block:: bash
export HDLMAKE_RSYNTH_USER=javi
export HDLMAKE_RSYNTH_SERVER=192.168.0.13
export HDLMAKE_RSYNTH_ISE_PATH=/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/
export HDLMAKE_RSYNTH_USE_SCREEN=1
Once this parameters are defined, we can use any of the available remote synthesis Makefile targets,
that are enumerated in the following table:
+-------------------------+---------------------------------------------------------------------+
| Remote Makefile Target | Target Description |
+=========================+=====================================================================+
| remote | Transfer required files to the remote server and run the synthesis |
+-------------------------+---------------------------------------------------------------------+
| sync | Copy back the synthesis outcomes in the server to the local folder |
+-------------------------+---------------------------------------------------------------------+
| cleanremote | Delete the remote synthesis folder to free space in the server |
+-------------------------+---------------------------------------------------------------------+
Incremental synthesis in Xilinx ISE
-----------------------------------
Note that, for both local and remote Xilinx ISE synthesis, the synthesis process in the Makefile generated by ``hdlmake``
performs the complete process by running a step-by-step approach that goes from synthesis to bitstream generation
instead of executing a single "build_all" command. Going through this step-by-step path, the synthesis process
scans for already performed ISE steps, so that only the pending ones are actually executed
(this information is stored in the associated .gise file).
The different Xilinx ISE steps that are performed by the synthesis makefile are:
- Synthesize - XST
- Translate
- Map
- Place & Route
- Generate Programming File
The main advantage of this approach is that, when synthesizing complex designs, the process can be resumed if
it fails or is halted and the already performed jobs don't need to be re-launched. The drawback is that a little time
overhead is introduced while scanning for the already completed stuff, and this can be noticed if the design is trivial.
If you want to re-synthesize the whole system from the start without scanning for already performed jobs,
just perform a ``make clean`` or ``make cleanremote`` before executing the ``make`` or ``make remote`` command.
Advanced examples Advanced examples
----------------- -----------------
**EVO project**: PlanAhead synthesis project for the Zedboard platform, powered by Xilinx Zynq based ARM Dual Cortex-A9 processor plus Artix grade FPGA and performing an asynchronous logic demo: **EVO project**: PlanAhead synthesis project for the Zedboard platform, powered by Xilinx Zynq based ARM Dual Cortex-A9 processor plus Artix grade FPGA and performing an asynchronous logic demo:
http://www.ohwr.org/projects/evo/repository http://www.ohwr.org/projects/evo/repository
**UMV, Mentor Questa & System Verilog simulation**: Work in progress, ready to be merged into Main branch. **UMV, Mentor Questa & System Verilog simulation**: A test example involving these tools and languages is included in the ``hdlmake`` source tree.
You can find it inside the ``tests/questa_uvm_sv`` folder.
hdlmake supported actions/commands hdlmake supported actions/commands
...@@ -633,7 +892,7 @@ hdlmake supported actions/commands ...@@ -633,7 +892,7 @@ hdlmake supported actions/commands
Check environment (``check-env``) Check environment (``check-env``)
--------------------------------- ---------------------------------
Check environment for HDLMAKE-related settings. This scan the top Manifest and report if the potentially used tools or/and environment variables are met or not. Check environment for HDLMake-related settings. This scan the top Manifest and report if the potentially used tools or/and environment variables are met or not.
Print manifest file variables description (``manifest-help``) Print manifest file variables description (``manifest-help``)
------------------------------------------------------------- -------------------------------------------------------------
...@@ -700,6 +959,8 @@ Automatic execution (``auto``) ...@@ -700,6 +959,8 @@ Automatic execution (``auto``)
------------------------------ ------------------------------
This is the default action for hdlmake, the one that is run when a command is not given. This is the default action for hdlmake, the one that is run when a command is not given.
.. note:: The ``auto`` command is just inferred if the issued command is a plain ``hdlmake``. If an optional argument is provided, you need to specify the specific command that is going to be executed.
The basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy top ``Manifest.py``. This can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be: The basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy top ``Manifest.py``. This can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be:
**simulation**: **simulation**:
...@@ -721,62 +982,148 @@ Manifest variables description ...@@ -721,62 +982,148 @@ Manifest variables description
Top Manifest variables Top Manifest variables
---------------------- ----------------------
action ; [<type 'str'>] ; What is the action that should be taken (simulation/synthesis), default="" +----------------+--------------+-----------------------------------------------------------------+-----------+
top_module ; [<type 'str'>] ; Top level entity for synthesis and simulation, default=None | Name | Type | Description | Default |
incl_makefiles ; [<type 'list'>, <type 'str'>]; List of .mk files appended to toplevel makefile, default=[] +================+==============+=================================================================+===========+
| action | str | What is the action that should be taken (simulation/synthesis) | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| top_module | str | Top level entity for synthesis and simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| incl_makefiles | list, str | List of .mk files appended to toplevel makefile | [] |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Universal variables Universal variables
------------------- -------------------
fetchto ; [<type 'str'>] ; Destination for fetched modules , default=None +----------------+--------------+-----------------------------------------------------------------+-----------+
modules ; [<type 'dict'>] ; List of local modules , default={} | Name | Type | Description | Default |
files ; [<type 'str'>, <type 'list'>]; List of files from the current module , default=[] +================+==============+=================================================================+===========+
library ; [<type 'str'>] ; Destination library for module's VHDL files , default=work | fetchto | str | Destination for fetched modules | None |
include_dirs ; [<type 'list'>, <type 'str'>]; Include dirs for Verilog sources , default=None +----------------+--------------+-----------------------------------------------------------------+-----------+
| modules | dict | List of local modules | {} |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| files | str, list | List of files from the current module | [] |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| library | str | Destination library for module's VHDL files | work |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| include_dirs | list, str | Include dirs for Verilog sources | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Simulation variables Simulation variables
-------------------- --------------------
sim_tool ; [<type 'str'>] ; Simulation tool to be used (e.g. isim, vsim, iverilog), default=None
sim_pre_cmd ; [<type 'str'>] ; Command to be executed before simulation , default=None
sim_post_cmd ; [<type 'str'>] ; Command to be executed after simulation , default=None
vsim_opt ; [<type 'str'>] ; Additional options for vsim , default=""
vcom_opt ; [<type 'str'>] ; Additional options for vcom , default=""
vlog_opt ; [<type 'str'>] ; Additional options for vlog , default=""
vmap_opt ; [<type 'str'>] ; Additional options for vmap , default=""
iverilog_opt ; [<type 'str'>] ; Additional options for iverilog , default="" Basic simulation variables:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| sim_tool | str | Simulation tool to be used (e.g. isim, vsim, iverilog) | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| sim_pre_cmd | str | Command to be executed before simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| sim_post_cmd | str | Command to be executed after simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Modelsim/VSim specific variables:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| vsim_opt | str | Additional options for vsim | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| vcom_opt | str | Additional options for vcom | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| vlog_opt | str | Additional options for vlog | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| vmap_opt | str | Additional options for vmap | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Icarus Verilog specific variables:
quartus_preflow; [<type 'str'>] ; Quartus pre-flow script file , default=None +----------------+--------------+-----------------------------------------------------------------+-----------+
quartus_postmodule; [<type 'str'>] ; Quartus post-module script file , default=None | Name | Type | Description | Default |
quartus_postflow; [<type 'str'>] ; Quartus post-flow script file , default=None +================+==============+=================================================================+===========+
| iverilog_opt | str | Additional options for iverilog | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
sim_only_files ; [<type 'list'>, <type 'str'>]; List of files that are used only in simulation, default=[]
bit_file_targets; [<type 'list'>, <type 'str'>]; List of files that are used only in simulation, default=[] Others:
+-------------------+-----------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+===================+===========+=================================================================+===========+
| sim_only_files | list, str | List of files that are used only in simulation | [] |
+-------------------+-----------+-----------------------------------------------------------------+-----------+
| bit_file_targets | list, str | List of files that are used only in simulation | [] |
+-------------------+-----------+-----------------------------------------------------------------+-----------+
Synthesis variables Synthesis variables
------------------- -------------------
target ; [<type 'str'>] ; What is the target architecture , default=""
syn_tool ; [<type 'str'>] ; Tool to be used in the synthesis , default=None Basic synthesis variables:
syn_device ; [<type 'str'>] ; Target FPGA device , default=None
syn_grade ; [<type 'str'>] ; Speed grade of target FPGA , default=None +-----------------+-------------+-----------------------------------------------------------------+-----------+
syn_package ; [<type 'str'>] ; Package variant of target FPGA , default=None | Name | Type | Description | Default |
syn_top ; [<type 'str'>] ; Top level module for synthesis , default=None +=================+=============+=================================================================+===========+
syn_project ; [<type 'str'>] ; Project file name , default=None | target | str | What is the target architecture | "" |
syn_ise_version; [<type 'type'>, <type 'str'>]; Force particular ISE version , default=None +-----------------+-------------+-----------------------------------------------------------------+-----------+
syn_pre_cmd ; [<type 'str'>] ; Command to be executed before synthesis , default=None | syn_tool | str | Tool to be used in the synthesis | None |
syn_post_cmd ; [<type 'str'>] ; Command to be executed after synthesis , default=None +-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_device | str | Target FPGA device | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_grade | str | Speed grade of target FPGA | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_package | str | Package variant of target FPGA | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_top | str | Top level module for synthesis | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_project | str | Project file name | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_cmd | str | Command to be executed before synthesis | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_cmd | str | Command to be executed after synthesis | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
Xilinx ISE specific variables:
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+=================+=============+=================================================================+===========+
| syn_ise_version | str | Force particular ISE version | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
Altera QuartusII specific variables:
+--------------------+----------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+====================+==========+=================================================================+===========+
| quartus_preflow | str | Quartus pre-flow script file | None |
+--------------------+----------+-----------------------------------------------------------------+-----------+
| quartus_postmodule | str | Quartus post-module script file | None |
+--------------------+----------+-----------------------------------------------------------------+-----------+
| quartus_postflow | str | Quartus post-flow script file | None |
+--------------------+----------+-----------------------------------------------------------------+-----------+
Miscellaneous variables Miscellaneous variables
----------------------- -----------------------
syn_name ; [<type 'str'>] ; Name of the folder at remote synthesis machine, default=None +-------------+-------+---------------------------------------------------------------------------+-----------+
force_tool ; [<type 'str'>] ; Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6, default=None | Name | Type | Description | Default |
+=============+=======+===========================================================================+===========+
| syn_name | str | Name of the folder at remote synthesis machine | None |
+-------------+-------+---------------------------------------------------------------------------+-----------+
| force_tool | str | Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6 | None |
+-------------+-------+---------------------------------------------------------------------------+-----------+
.. _args: .. _args:
...@@ -830,4 +1177,10 @@ http://www.ohwr.org/projects/fpga-config-space/wiki ...@@ -830,4 +1177,10 @@ http://www.ohwr.org/projects/fpga-config-space/wiki
Force hdlmake to generate the makefile, even if the specified tool is missing. Force hdlmake to generate the makefile, even if the specified tool is missing.
``--allow-unknown``
--------------------------
.. warning:: this is an experimental feature!!
Allow the insertion of new options or variables inside the child Manifest. Is this is option is not specified, the only place in which new options or variables can be defined is the top Manifest.
hdlmake/__main__.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -103,9 +103,21 @@ def main(): ...@@ -103,9 +103,21 @@ def main():
# #
# Load global tool object (global_mod.py) # Load global tool object (global_mod.py)
# #
if not top_mod.action:
logging.error("`action' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to handle the project")
quit()
if top_mod.action == "synthesis": if top_mod.action == "synthesis":
if not top_mod.syn_tool:
logging.error("`syn_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to synthesize the project")
quit()
tool_name = top_mod.syn_tool tool_name = top_mod.syn_tool
elif top_mod.action == "simulation": elif top_mod.action == "simulation":
if not top_mod.sim_tool:
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project")
quit()
tool_name = top_mod.sim_tool tool_name = top_mod.sim_tool
logging.info('import tool module: ' + tool_name) logging.info('import tool module: ' + tool_name)
try: try:
...@@ -209,7 +221,7 @@ def _get_parser(): ...@@ -209,7 +221,7 @@ def _get_parser():
""" """
usage = """hdlmake [command] [options]""" usage = """hdlmake [command] [options]"""
description = """Release 2014\n description = """Version 2.1\n
To see optional arguments for particular command type: To see optional arguments for particular command type:
hdlmake <command> --help hdlmake <command> --help
\0 \0
...@@ -265,6 +277,9 @@ def _get_parser(): ...@@ -265,6 +277,9 @@ def _get_parser():
parser.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project", parser.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project",
dest="generate_project_vhd", default=False, action="store_true") dest="generate_project_vhd", default=False, action="store_true")
parser.add_argument("--force", help="force hdlmake to generate the makefile, even if the specified tool is missing", default=False, action="store_true") parser.add_argument("--force", help="force hdlmake to generate the makefile, even if the specified tool is missing", default=False, action="store_true")
parser.add_argument("--allow-unknown", dest="allow_unknown",
default=False, help="allow unknown option insertions in the child Manifests", action="store_true")
return parser return parser
......
hdlmake/action/remote_synthesis.py
View file @ d342f521
...@@ -49,29 +49,29 @@ class GenerateRemoteSynthesisMakefile(Action): ...@@ -49,29 +49,29 @@ class GenerateRemoteSynthesisMakefile(Action):
self._generate_remote_synthesis_makefile(tool_object) self._generate_remote_synthesis_makefile(tool_object)
def _search_tcl_file(self, directory=None): #def _search_tcl_file(self, directory=None):
# This function is used in _generate_remote_ise_makefile # # This function is used in _generate_remote_ise_makefile
if directory is None: # if directory is None:
directory = "." # directory = "."
filenames = os.listdir(directory) # filenames = os.listdir(directory)
tcls = [] # tcls = []
for filename in filenames: # for filename in filenames:
file_parts = filename.split('.') # file_parts = filename.split('.')
if file_parts[len(file_parts)-1] == "tcl": # if file_parts[len(file_parts)-1] == "tcl":
tcls.append(filename) # tcls.append(filename)
if len(tcls) == 0: # if len(tcls) == 0:
return None # return None
if len(tcls) > 1: # if len(tcls) > 1:
logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" + # logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
"Picking the first one: " + tcls[0]) # "Picking the first one: " + tcls[0])
return tcls[0] # return tcls[0]
def _generate_tcl(self): #def _generate_tcl(self):
# This function is used in _generate_remote_ise_makefile # # This function is used in _generate_remote_ise_makefile
f = open("run.tcl", "w") # f = open("run.tcl", "w")
f.write("project open " + self.top_module.syn_project + '\n') # f.write("project open " + self.top_module.syn_project + '\n')
f.write("process run {Generate Programming File} -force rerun_all\n") # f.write("process run {Generate Programming File} -force rerun_all\n")
f.close() # f.close()
def _generate_remote_synthesis_makefile(self, tool_object): def _generate_remote_synthesis_makefile(self, tool_object):
...@@ -80,14 +80,14 @@ class GenerateRemoteSynthesisMakefile(Action): ...@@ -80,14 +80,14 @@ class GenerateRemoteSynthesisMakefile(Action):
top_mod = self.modules_pool.get_top_module() top_mod = self.modules_pool.get_top_module()
tcl = self._search_tcl_file() #tcl = self._search_tcl_file()
if tcl is None: #if tcl is None:
self._generate_tcl() # self._generate_tcl()
tcl = "run.tcl" # tcl = "run.tcl"
files = self.modules_pool.build_global_file_set() files = self.modules_pool.build_global_file_set()
sff = SourceFileFactory() sff = SourceFileFactory()
files.add(sff.new(tcl, module=None)) files.add(sff.new("run.tcl", module=None))
files.add(sff.new(top_mod.syn_project, module=None)) files.add(sff.new(top_mod.syn_project, module=None))
tool_object.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name, tool_object.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
......
hdlmake/action/synthesis_project.py
View file @ d342f521
...@@ -148,7 +148,7 @@ end sdb_meta_pkg;""") ...@@ -148,7 +148,7 @@ end sdb_meta_pkg;""")
env = self.env env = self.env
if not self.options.force: if not self.options.force:
if self.env[path_key] is None: if self.env[path_key] is None:
logging.error("Can't generate an " + name + " project. " + name + " not found.") logging.error("Can't generate the " + name + " project. " + name + " not found.")
quit() quit()
if not env[version_key]: if not env[version_key]:
logging.error(name + " version cannot be deduced. Cannot generate " + name + " " logging.error(name + " version cannot be deduced. Cannot generate " + name + " "
......
hdlmake/module.py
View file @ d342f521
...@@ -207,7 +207,10 @@ class Module(object): ...@@ -207,7 +207,10 @@ class Module(object):
allow_unknown = True allow_unknown = True
extra_context = {} extra_context = {}
else: else:
allow_unknown = False if global_mod.options.allow_unknown is True:
allow_unknown = True
else:
allow_unknown = False
extra_context = dict(global_mod.top_module.manifest_dict) # copy the dictionary extra_context = dict(global_mod.top_module.manifest_dict) # copy the dictionary
del extra_context["modules"] del extra_context["modules"]
del extra_context["files"] del extra_context["files"]
......
hdlmake/srcfile.py
View file @ d342f521
...@@ -38,11 +38,16 @@ class SourceFile(DepFile): ...@@ -38,11 +38,16 @@ class SourceFile(DepFile):
assert isinstance(path, basestring) assert isinstance(path, basestring)
assert isinstance(module, Module) assert isinstance(module, Module)
self.library = library self.library = library
if not library:
self.library = "work"
DepFile.__init__(self, DepFile.__init__(self,
file_path=path, file_path=path,
module=module, module=module,
include_paths=module.include_dirs[:]) include_paths=module.include_dirs[:])
def __hash__(self):
return hash(self.path + self.library)
class VHDLFile(SourceFile): class VHDLFile(SourceFile):
def __init__(self, path, module, library=None, vcom_opt=None): def __init__(self, path, module, library=None, vcom_opt=None):
...@@ -64,8 +69,6 @@ class VHDLFile(SourceFile): ...@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
class VerilogFile(SourceFile): class VerilogFile(SourceFile):
def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None): def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
if not library:
library = "work"
SourceFile.__init__(self, path=path, module=module, library=library) SourceFile.__init__(self, path=path, module=module, library=library)
if not vlog_opt: if not vlog_opt:
self.vlog_opt = "" self.vlog_opt = ""
...@@ -122,6 +125,14 @@ class PPRFile(File): ...@@ -122,6 +125,14 @@ class PPRFile(File):
# Xilinx PlanAhead Project # Xilinx PlanAhead Project
pass pass
class XPRFile(File):
# Xilinx Vivado Project
pass
class BDFile(File):
# Xilinx Block Design
pass
class XCOFile(File): class XCOFile(File):
# Xilinx Core Generator File # Xilinx Core Generator File
pass pass
...@@ -251,6 +262,10 @@ class SourceFileFactory: ...@@ -251,6 +262,10 @@ class SourceFileFactory:
nf = XMPFile(path=path, module=module) nf = XMPFile(path=path, module=module)
elif extension == 'ppr': elif extension == 'ppr':
nf = PPRFile(path=path, module=module) nf = PPRFile(path=path, module=module)
elif extension == 'xpr':
nf = XPRFile(path=path, module=module)
elif extension == 'bd':
nf = BDFile(path=path, module=module)
elif extension == 'xco': elif extension == 'xco':
nf = XCOFile(path=path, module=module) nf = XCOFile(path=path, module=module)
elif extension == 'ldf': elif extension == 'ldf':
......
hdlmake/tools/aldec/aldec.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -56,7 +56,9 @@ run.command \ ...@@ -56,7 +56,9 @@ run.command \
library.cfg library.cfg
#target for performing local simulation #target for performing local simulation
sim: sim_pre_cmd local: sim_pre_cmd simulation sim_post_cmd
simulation:
""") """)
makefile_text_1 = makefile_tmplt_1.substitute( makefile_text_1 = makefile_tmplt_1.substitute(
top_module=top_module.top_module top_module=top_module.top_module
...@@ -86,7 +88,7 @@ sim: sim_pre_cmd ...@@ -86,7 +88,7 @@ sim: sim_pre_cmd
sim_pre_cmd: sim_pre_cmd:
\t\t${sim_pre_cmd} \t\t${sim_pre_cmd}
sim_post_cmd: sim sim_post_cmd:
\t\t${sim_post_cmd} \t\t${sim_post_cmd}
#target for cleaning all intermediate stuff #target for cleaning all intermediate stuff
...@@ -97,7 +99,7 @@ clean: ...@@ -97,7 +99,7 @@ clean:
mrproper: clean mrproper: clean
\t\trm -f *.vcd *.asdb \t\trm -f *.vcd *.asdb
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd .PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""") """)
......
hdlmake/tools/common/__init__.py 0 → 100644
View file @ d342f521
"""Common functionality shared by multiple tools."""
hdlmake/tools/common/sim_makefile_support.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from makefile_writer import MakefileWriter
import os
import string
from string import Template
class VsimMakefileWriter(MakefileWriter):
"""A Makefile writer for simulation suitable for vsim based simulators.
Currently used by:
- Modelsim
- Riviera
"""
def __init__(self):
# additional global flags to pass to every invocation of these commands
self.vcom_flags = ["-quiet", ]
self.vsim_flags = []
self.vlog_flags = ["-quiet", ]
self.vmap_flags = []
# These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value
self.custom_variables = {}
# Additional sim dependencies (e.g. modelsim.ini)
self.additional_deps = []
# Additional things removed during a clean e.g. simulator temp files
self.additional_clean = []
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
def generate_simulation_makefile(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from srcfile import VerilogFile, VHDLFile, SVFile
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
tmp = """## variables #############################
PWD := $(shell pwd)
"""
self.write(tmp)
self.writeln()
for var, value in self.custom_variables.iteritems():
self.writeln("%s := %s" % (var, value))
self.writeln()
self.writeln("VCOM_FLAGS := %s" % (' '.join(self.vcom_flags)))
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(os.path.join(vl.library, vl.purename, "." + vl.purename + "_" + vl.extension()) + " \\\n")
self.write('\n')
libs = set(f.library for f in fileset)
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(os.path.join(vhdl.library, vhdl.purename, "." + vhdl.purename + "_" + vhdl.extension()) + " \\\n")
self.write('\n')
self.write('LIBS := ')
self.write(' '.join(libs))
self.write('\n')
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + "/." + lib for lib in libs]))
self.write('\n')
self.writeln("## rules #################################")
self.writeln()
self.writeln("local: sim_pre_cmd simulation sim_post_cmd")
self.writeln()
self.writeln("simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" % (' '.join(self.additional_deps)),)
self.writeln("$(VERILOG_OBJ) : " + ' '.join(self.additional_deps))
self.writeln("$(VHDL_OBJ): $(LIB_IND) " + ' '.join(self.additional_deps))
self.writeln()
simcommands = string.Template("""sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
simcommands = simcommands.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.write(simcommands)
self.writeln()
for filename, filesource in self.copy_rules.iteritems():
self.write(self.__create_copy_rule(filename, filesource))
self.writeln("clean:")
tmp = "\t\trm -rf $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln(".PHONY: clean sim_pre_cmd sim_post_cmd simulation")
self.writeln()
for lib in libs:
self.write(lib + "/." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + "/." + lib, ")"]))
self.write(' '.join(["||", "rm -rf", lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
# ##
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template = Template("\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option="-sv" if isinstance(vl, SVFile) else "",
include_dirs='+'.join(vl.include_dirs),
vlog_opt=vl.vlog_opt)
self.writeln(compile_line)
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path())
)
for dep_file in vhdl.depends_on:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@ \n")
self.writeln()
def __create_copy_rule(self, name, src):
"""Get a Makefile rule named name, which depends on src, copying it to
the local directory."""
rule = """%s: %s
\t\tcp $< . 2>&1
""" % (name, src)
return rule
def __get_rid_of_vsim_incdirs(self, vlog_opt=""):
if not vlog_opt:
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
return ' '.join(ret)
hdlmake/tools/diamond/diamond.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -61,7 +61,9 @@ $$(PROJECT)1.sty \ ...@@ -61,7 +61,9 @@ $$(PROJECT)1.sty \
run.tcl run.tcl
#target for performing local synthesis #target for performing local synthesis
local: syn_pre_cmd check_tool local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "prj_project open \"$$(PROJECT).ldf\"" > run.tcl \t\techo "prj_project open \"$$(PROJECT).ldf\"" > run.tcl
\t\techo "prj_run PAR -impl $$(PROJECT)" >> run.tcl \t\techo "prj_run PAR -impl $$(PROJECT)" >> run.tcl
\t\techo "prj_run Export -impl $$(PROJECT) -task Bitgen" >> run.tcl \t\techo "prj_run Export -impl $$(PROJECT) -task Bitgen" >> run.tcl
...@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool ...@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool
check_tool: check_tool:
\t\t${check_tool} \t\t${check_tool}
syn_post_cmd: local syn_post_cmd:
\t\t${syn_post_cmd} \t\t${syn_post_cmd}
syn_pre_cmd: syn_pre_cmd:
...@@ -87,7 +89,7 @@ clean: ...@@ -87,7 +89,7 @@ clean:
mrproper: mrproper:
\t\trm -f *.jed \t\trm -f *.jed
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""") """)
if top_mod.syn_pre_cmd: if top_mod.syn_pre_cmd:
......
hdlmake/tools/ghdl/ghdl.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -61,7 +61,9 @@ GHDL_CRAP := \ ...@@ -61,7 +61,9 @@ GHDL_CRAP := \
#target for performing local simulation #target for performing local simulation
sim: sim_pre_cmd local: sim_pre_cmd simulation sim_post_cmd
simulation:
""") """)
makefile_text_1 = makefile_tmplt_1.substitute( makefile_text_1 = makefile_tmplt_1.substitute(
...@@ -82,7 +84,7 @@ sim: sim_pre_cmd ...@@ -82,7 +84,7 @@ sim: sim_pre_cmd
sim_pre_cmd: sim_pre_cmd:
\t\t${sim_pre_cmd} \t\t${sim_pre_cmd}
sim_post_cmd: sim sim_post_cmd:
\t\t${sim_post_cmd} \t\t${sim_post_cmd}
#target for cleaning all intermediate stuff #target for cleaning all intermediate stuff
...@@ -93,7 +95,7 @@ clean: ...@@ -93,7 +95,7 @@ clean:
mrproper: clean mrproper: clean
\t\trm -f *.vcd \t\trm -f *.vcd
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd .PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""") """)
......
hdlmake/tools/ise/ise.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -48,6 +48,8 @@ FAMILY_NAMES = { ...@@ -48,6 +48,8 @@ FAMILY_NAMES = {
"XC6V": "Virtex6", "XC6V": "Virtex6",
"XC5V": "Virtex5", "XC5V": "Virtex5",
"XC4V": "Virtex4", "XC4V": "Virtex4",
"XC7Z": "Zynq",
"XC7V": "Virtex7",
"XC7K": "Kintex7", "XC7K": "Kintex7",
"XC7A": "Artix7"} "XC7A": "Artix7"}
...@@ -116,23 +118,23 @@ class ToolControls(MakefileWriter): ...@@ -116,23 +118,23 @@ class ToolControls(MakefileWriter):
remote_name_tmpl = "R_NAME:={0}" remote_name_tmpl = "R_NAME:={0}"
files_tmpl = "FILES := {0}" files_tmpl = "FILES := {0}"
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)#take the value from the environment") user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)# take the value from the environment")
test_tmpl = """__test_for_remote_synthesis_variables: test_tmpl = """__test_for_remote_synthesis_variables:
ifeq (x$(USER),x) ifeq (x$(USER),x)
\t@echo "Remote synthesis user is not set.\ \t@echo "Remote synthesis user is not set. \
You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif endif
ifeq (x$(SERVER),x) ifeq (x$(SERVER),x)
\t@echo "Remote synthesis server is not set.\ \t@echo "Remote synthesis server is not set. \
You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif endif
ifeq (x$(ISE_PATH),x) ifeq (x$(ISE_PATH),x)
\t@echo "Remote synthesis server is not set.\ \t@echo "Remote synthesis server is not set. \
You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif endif
""" """
if server is None: if server is None:
server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)#take the value from the environment") server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment")
else: else:
server_tmpl = server_tmpl.format(server) server_tmpl = server_tmpl.format(server)
...@@ -150,7 +152,7 @@ endif ...@@ -150,7 +152,7 @@ endif
self.writeln(files_tmpl.format(' \\\n'.join([s.rel_path() for s in files]))) self.writeln(files_tmpl.format(' \\\n'.join([s.rel_path() for s in files])))
self.writeln("") self.writeln("")
self.writeln("#target for running synthesis in the remote location") self.writeln("#target for running synthesis in the remote location")
self.writeln("remote: __test_for_remote_synthesis_variables __send __do_synthesis") self.writeln("remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis")
self.writeln("__send_back: __do_synthesis") self.writeln("__send_back: __do_synthesis")
self.writeln("__do_synthesis: __send") self.writeln("__do_synthesis: __send")
self.writeln("__send: __test_for_remote_synthesis_variables") self.writeln("__send: __test_for_remote_synthesis_variables")
...@@ -235,21 +237,29 @@ webtalk_pn.xml \ ...@@ -235,21 +237,29 @@ webtalk_pn.xml \
run.tcl run.tcl
#target for performing local synthesis #target for performing local synthesis
local: syn_pre_cmd check_tool local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
\t\techo "project open $$(PROJECT)" > run.tcl \t\techo "project open $$(PROJECT)" > run.tcl
\t\techo "process run {Generate Programming File} -force rerun_all" >> run.tcl \t\techo "process run {Synthesize - XST}" >> run.tcl
\t\techo "process run {Translate}" >> run.tcl
\t\techo "process run {Map}" >> run.tcl
\t\techo "process run {Place & Route}" >> run.tcl
\t\techo "process run {Generate Programming File}" >> run.tcl
synthesis:
\t\t${xtclsh_path} run.tcl \t\t${xtclsh_path} run.tcl
check_tool: check_tool:
\t\t${check_tool} \t\t${check_tool}
syn_post_cmd: local syn_post_cmd:
\t\t${syn_post_cmd} \t\t${syn_post_cmd}
syn_pre_cmd: syn_pre_cmd:
\t\t${syn_pre_cmd} \t\t${syn_pre_cmd}
#target for cleaing all intermediate stuff #target for cleaning all intermediate stuff
clean: clean:
\t\trm -f $$(ISE_CRAP) \t\trm -f $$(ISE_CRAP)
\t\trm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo \t\trm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
...@@ -258,7 +268,7 @@ clean: ...@@ -258,7 +268,7 @@ clean:
mrproper: mrproper:
\t\trm -f *.bit *.bin *.mcs \t\trm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local check_tool .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""") """)
if top_mod.syn_pre_cmd: if top_mod.syn_pre_cmd:
......
hdlmake/tools/isim/isim.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br) # Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br) # Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
...@@ -86,14 +86,16 @@ ISIM_FLAGS := ...@@ -86,14 +86,16 @@ ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """
""" """
make_preambule_p2 = string.Template("""## rules ################################# make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse local: sim_pre_cmd simulation sim_post_cmd
simulation: xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
$$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini $$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini
$$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini $$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini
sim_pre_cmd: sim_pre_cmd:
\t\t${sim_pre_cmd} \t\t${sim_pre_cmd}
sim_post_cmd: sim sim_post_cmd:
\t\t${sim_post_cmd} \t\t${sim_post_cmd}
xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini
...@@ -104,7 +106,7 @@ fuse: ...@@ -104,7 +106,7 @@ fuse:
clean: clean:
\t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \ \t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.* isim.wdb isim_proj isim_proj.*
.PHONY: clean sim_pre_cmd sim_post_cmd .PHONY: clean sim_pre_cmd sim_post_cmd simulation
""") """)
#open the file and write the above preambule (part 1) #open the file and write the above preambule (part 1)
......
hdlmake/tools/iverilog/iverilog.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -70,10 +70,13 @@ class ToolControls(MakefileWriter): ...@@ -70,10 +70,13 @@ class ToolControls(MakefileWriter):
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module} makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
IVERILOG_CRAP := \ IVERILOG_CRAP := \
run.command run.command \
ivl_vhdl_work
#target for performing local simulation #target for performing local simulation
sim: sim_pre_cmd local: sim_pre_cmd simulation sim_post_cmd
simulation:
""") """)
makefile_text_1 = makefile_tmplt_1.substitute( makefile_text_1 = makefile_tmplt_1.substitute(
...@@ -99,7 +102,7 @@ sim: sim_pre_cmd ...@@ -99,7 +102,7 @@ sim: sim_pre_cmd
sim_pre_cmd: sim_pre_cmd:
\t\t${sim_pre_cmd} \t\t${sim_pre_cmd}
sim_post_cmd: sim sim_post_cmd:
\t\t${sim_post_cmd} \t\t${sim_post_cmd}
#target for cleaning all intermediate stuff #target for cleaning all intermediate stuff
...@@ -110,7 +113,7 @@ clean: ...@@ -110,7 +113,7 @@ clean:
mrproper: clean mrproper: clean
\t\trm -f *.vcd *.vvp \t\trm -f *.vcd *.vvp
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd .PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""") """)
if top_module.sim_pre_cmd: if top_module.sim_pre_cmd:
......
hdlmake/tools/libero/libero.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -61,7 +61,9 @@ LIBERO_CRAP := \ ...@@ -61,7 +61,9 @@ LIBERO_CRAP := \
run.tcl run.tcl
#target for performing local synthesis #target for performing local synthesis
local: syn_pre_cmd check_tool local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project -file {$$(PROJECT)/$$(PROJECT).prjx}" > run.tcl \t\techo "open_project -file {$$(PROJECT)/$$(PROJECT).prjx}" > run.tcl
\t\techo "update_and_run_tool -name {GENERATEPROGRAMMINGDATA}" >> run.tcl \t\techo "update_and_run_tool -name {GENERATEPROGRAMMINGDATA}" >> run.tcl
\t\techo "save_project" >> run.tcl \t\techo "save_project" >> run.tcl
...@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool ...@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool
check_tool: check_tool:
\t\t${check_tool} \t\t${check_tool}
syn_post_cmd: local syn_post_cmd:
\t\t${syn_post_cmd} \t\t${syn_post_cmd}
syn_pre_cmd: syn_pre_cmd:
...@@ -87,7 +89,7 @@ clean: ...@@ -87,7 +89,7 @@ clean:
mrproper: mrproper:
\t\trm -f *.pdb *.stp \t\trm -f *.pdb *.stp
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""") """)
if top_mod.syn_pre_cmd: if top_mod.syn_pre_cmd:
......
hdlmake/tools/modelsim/modelsim.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -33,15 +33,16 @@ import string ...@@ -33,15 +33,16 @@ import string
from string import Template from string import Template
import fetch import fetch
from makefile_writer import MakefileWriter from .. common.sim_makefile_support import VsimMakefileWriter
XmlImpl = xml.dom.minidom.getDOMImplementation() XmlImpl = xml.dom.minidom.getDOMImplementation()
MODELSIM_STANDARD_LIBS = ['ieee', 'std'] MODELSIM_STANDARD_LIBS = ['ieee', 'std']
class ToolControls(MakefileWriter): class ToolControls(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
def detect_version(self, path): def detect_version(self, path):
pass pass
...@@ -60,164 +61,17 @@ class ToolControls(MakefileWriter): ...@@ -60,164 +61,17 @@ class ToolControls(MakefileWriter):
return MODELSIM_STANDARD_LIBS return MODELSIM_STANDARD_LIBS
def generate_simulation_makefile(self, fileset, top_module): def generate_simulation_makefile(self, fileset, top_module):
from srcfile import VerilogFile, VHDLFile, SVFile self.vcom_flags.extend(["-modelsimini", "modelsim.ini"])
make_preambule_p1 = """## variables ############################# self.vlog_flags.extend(["-modelsimini", "modelsim.ini"])
PWD := $(shell pwd) self.vmap_flags.extend(["-modelsimini", "modelsim.ini"])
MODELSIM_INI_PATH := {0}
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_vsim_incdirs(top_module.vlog_opt) + """
"""
if global_mod.env["modelsim_path"]: if global_mod.env["modelsim_path"]:
make_preambule_p1 = make_preambule_p1.format(os.path.join(global_mod.env["modelsim_path"], "..")) modelsim_ini_path = os.path.join(global_mod.env["modelsim_path"], "..")
else: else:
make_preambule_p1 = make_preambule_p1.format(os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")) modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
make_preambule_p2 = string.Template("""## rules ################################# self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) self.additional_deps.append("modelsim.ini")
$$(VERILOG_OBJ): $$(VHDL_OBJ) self.additional_clean.extend(["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
\t\t${sim_post_cmd}
modelsim.ini: ${modelsim_ini_path}
\t\tcp $$< . 2>&1
clean:
\t\trm -rf ./modelsim.ini $$(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd
""")
#open the file and write the above preambule (part 1)
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
#make a file compilation indicator (these .dat files are made even if
#the compilation process fails) and add an ending according to file's
#extension (.sv and .vhd files may have the same corename and this
#causes a mess
self.write(os.path.join(vl.library, vl.purename, "."+vl.purename+"_"+vl.extension()) + " \\\n")
self.write('\n')
libs = set(f.library for f in fileset)
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
#list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
#file compilation indicator (important: add _vhd ending)
self.write(os.path.join(vhdl.library, vhdl.purename, "."+vhdl.purename+"_"+vhdl.extension()) + " \\\n")
self.write('\n')
self.write('LIBS := ')
self.write(' '.join(libs))
self.write('\n')
#tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib+"/."+lib for lib in libs]))
self.write('\n')
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
make_preambule_p2 = make_preambule_p2.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
modelsim_ini_path=os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini"))
self.write(make_preambule_p2)
for lib in libs:
self.write(lib+"/."+lib+":\n")
self.write(' '.join(["\t(vlib", lib, "&&", "vmap", "-modelsimini modelsim.ini",
lib, "&&", "touch", lib+"/."+lib, ")"]))
self.write(' '.join(["||", "rm -rf", lib, "\n"]))
self.write('\n')
#rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
###
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template = Template("\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option = "-sv" if isinstance(vl, SVFile) else "",
include_dirs='+'.join(vl.include_dirs),
vlog_opt=vl.vlog_opt)
self.writeln(compile_line)
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
#list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
#each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "."+purename+"_" + vhdl.extension()),
vhdl.rel_path())
)
for dep_file in vhdl.depends_on:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
self.writeln()
def __get_rid_of_vsim_incdirs(self, vlog_opt): self.copy_rules["modelsim.ini"] = os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini")
if not vlog_opt: super(ToolControls, self).generate_simulation_makefile(fileset, top_module)
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
return ' '.join(ret)
hdlmake/tools/planahead/planahead.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -64,7 +64,9 @@ planAhead.* \ ...@@ -64,7 +64,9 @@ planAhead.* \
run.tcl run.tcl
#target for performing local synthesis #target for performing local synthesis
local: syn_pre_cmd check_tool local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project $$(PROJECT).ppr" > run.tcl \t\techo "open_project $$(PROJECT).ppr" > run.tcl
\t\techo "reset_run synth_1" >> run.tcl \t\techo "reset_run synth_1" >> run.tcl
\t\techo "reset_run impl_1" >> run.tcl \t\techo "reset_run impl_1" >> run.tcl
...@@ -81,7 +83,7 @@ local: syn_pre_cmd check_tool ...@@ -81,7 +83,7 @@ local: syn_pre_cmd check_tool
check_tool: check_tool:
\t\t${check_tool} \t\t${check_tool}
syn_post_cmd: local syn_post_cmd:
\t\t${syn_post_cmd} \t\t${syn_post_cmd}
syn_pre_cmd: syn_pre_cmd:
...@@ -96,7 +98,7 @@ clean: ...@@ -96,7 +98,7 @@ clean:
mrproper: mrproper:
\t\trm -f *.bit \t\trm -f *.bit
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""") """)
if top_mod.syn_pre_cmd: if top_mod.syn_pre_cmd:
......
hdlmake/tools/quartus/quartus.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013, 2014 CERN # Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch) # Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# #
...@@ -73,7 +73,9 @@ $$(PROJECT).sta.summary \ ...@@ -73,7 +73,9 @@ $$(PROJECT).sta.summary \
run.tcl run.tcl
#target for performing local synthesis #target for performing local synthesis
local: syn_pre_cmd check_tool local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "load_package flow" > run.tcl \t\techo "load_package flow" > run.tcl
\t\techo "project_open $$(PROJECT)" >> run.tcl \t\techo "project_open $$(PROJECT)" >> run.tcl
\t\techo "execute_flow -compile" >> run.tcl \t\techo "execute_flow -compile" >> run.tcl
...@@ -82,7 +84,7 @@ local: syn_pre_cmd check_tool ...@@ -82,7 +84,7 @@ local: syn_pre_cmd check_tool
check_tool: check_tool:
\t\t${check_tool} \t\t${check_tool}
syn_post_cmd: local syn_post_cmd:
\t\t${syn_post_cmd} \t\t${syn_post_cmd}
syn_pre_cmd: syn_pre_cmd:
...@@ -97,7 +99,7 @@ clean: ...@@ -97,7 +99,7 @@ clean:
mrproper: mrproper:
\t\trm -f *.sof *.pof *.jam *.jbc *.ekp *.jic \t\trm -f *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""") """)
if top_mod.syn_pre_cmd: if top_mod.syn_pre_cmd:
......
hdlmake/tools/riviera/riviera.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# Riviera tool added by Josh Smith (joshrsmith@gmail.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from __future__ import print_function
from .. common.sim_makefile_support import VsimMakefileWriter
# as of 2014.06, these are the standard libraries
# included in an installation
RIVIERA_STANDARD_LIBS = [
'ieee', 'std', 'cpld',
'vl', 'vital95', 'vital2000',
'synopsys', 'aldec', 'vtl',
'vtl_dbg', 'assertions', 'ieee_proposed',
'ovm_2_0_3', 'ovm_2_1_2', 'uvm_1_0p1',
'uvm_1_1d', 'uvm', 'osvvm',
]
# there are many vendor specific libraries available
# a few of them are listed here
RIVIERA_XILINX_VHDL_LIBRARIES = [
'cpld',
'secureip',
'simprim',
'unimacro',
'unisim',
'xilinxcorelib'
]
RIVIERA_XILINX_VLOG_LIBRARIES = [
'cpld_ver',
'secureip',
'simprims_ver',
'uni9000_ver',
'unimacro_ver',
'unisims_ver',
'xilinxcorelib_ver'
]
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES)
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolControls(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
self.vcom_flags.append("-2008")
self.additional_clean.extend(["*.asdb", "*.vcd", ])
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Riviera',
'id': 'riviera',
'windows_bin': 'vsim',
'linux_bin': 'vsim'
}
return tool_info
def get_standard_libraries(self):
return RIVIERA_STANDARD_LIBS
hdlmake/tools/vivado/vivado.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
import subprocess
import sys
import os
import string
from string import Template
import fetch
import logging
from makefile_writer import MakefileWriter
VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolControls(MakefileWriter):
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'vivado',
'id': 'vivado',
'windows_bin': 'vivado',
'linux_bin': 'vivado',
'project_ext': 'xpr'
}
return tool_info
def get_standard_libraries(self):
return VIVADO_STANDARD_LIBS
def generate_synthesis_makefile(self, top_mod, tool_path):
makefile_tmplt = string.Template("""PROJECT := ${project_name}
VIVADO_CRAP := \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project $$(PROJECT).xpr" > run.tcl
\t\techo "reset_run synth_1" >> run.tcl
\t\techo "reset_run impl_1" >> run.tcl
\t\techo "launch_runs synth_1" >> run.tcl
\t\techo "wait_on_run synth_1" >> run.tcl
\t\techo "launch_runs impl_1" >> run.tcl
\t\techo "wait_on_run impl_1" >> run.tcl
\t\techo "launch_runs impl_1 -to_step write_bitstream" >> run.tcl
\t\techo "wait_on_run impl_1" >> run.tcl
\t\techo "exit" >> run.tcl
\t\t${vivado_sh_path} -mode tcl -source run.tcl
\t\tcp $$(PROJECT).runs/impl_1/${syn_top}.bit ${syn_top}.bit
check_tool:
\t\t${check_tool}
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
\t\t${syn_pre_cmd}
#target for cleaning all intermediate stuff
clean:
\t\trm -f $$(PLANAHEAD_CRAP)
\t\trm -rf .Xil $$(PROJECT).cache $$(PROJECT).data $$(PROJECT).runs $$(PROJECT).xpr
#target for cleaning final files
mrproper:
\t\trm -f *.bit
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
syn_pre_cmd = top_mod.syn_pre_cmd
else:
syn_pre_cmd = ''
if top_mod.syn_post_cmd:
syn_post_cmd = top_mod.syn_post_cmd
else:
syn_post_cmd = ''
if top_mod.force_tool:
ft = top_mod.force_tool
check_tool = """python $(HDLMAKE_HDLMAKE_PATH)/hdlmake _conditioncheck --tool {tool} --reference {reference} --condition "{condition}"\\
|| (echo "{tool} version does not meet condition: {condition} {reference}" && false)
""".format(tool=ft[0],
condition=ft[1],
reference=ft[2])
else:
check_tool = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.syn_top,
project_name=top_mod.syn_project,
planahead_path=tool_path,
check_tool=check_tool,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
vivado_sh_path=os.path.join(tool_path, "vivado"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
logging.info("Remote Vivado wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
self.filename = top_mod.syn_project
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
logging.info("Existing project detected: updating...")
self.update_project()
else:
logging.info("No previous project: creating a new one...")
self.create_project()
self.add_initial_properties(top_mod.syn_device,
top_mod.syn_grade,
top_mod.syn_package,
top_mod.syn_top)
self.add_files(fileset)
self.emit()
self.execute()
logging.info("Vivado project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header+'\n')
for p in self.properties:
f.write(p.emit()+'\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
f.write('exit\n')
f.close()
def execute(self):
tmp = 'vivado -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till Vivado finish, start displaying output immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
def add_property(self, new_property):
self.properties.append(new_property)
def add_initial_properties(self,
syn_device,
syn_grade,
syn_package,
syn_top):
PAPP = _VivadoProjectProperty
self.add_property(PAPP(name='part', value=syn_device+syn_package+syn_grade, objects='current_project'))
# self.add_property(PAPP(name='board_part', value='em.avnet.com:microzed_7010:part0:1.0', objects='current_project'))
self.add_property(PAPP(name='target_language', value='VHDL', objects='current_project'))
# self.add_property(PAPP(name='ng.output_hdl_format', value='VHDL', objects='get_filesets sim_1'))
# the bitgen b arg generates a raw configuration bitstream
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true', objects='get_runs impl_1'))
self.add_property(PAPP(name='top', value=syn_top, objects='get_property srcset [current_run]'))
def create_project(self):
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
def update_project(self):
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename+'.xpr')
def __emit_properties(self):
tmp = "set_property {0} {1} [{2}]"
ret = []
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
ret.append(line)
return ('\n'.join(ret))+'\n'
def __emit_files(self):
tmp = "add_files -norecurse {0}"
tcl = "source {0}"
ret = []
from srcfile import VHDLFile, VerilogFile, SVFile, UCFFile, NGCFile, XMPFile, XCOFile, BDFile, TCLFile
for f in self.files:
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, UCFFile) or isinstance(f, NGCFile) or isinstance(f, XMPFile) or isinstance(f, XCOFile) or isinstance(f, BDFile):
line = tmp.format(f.rel_path())
elif isinstance(f, TCLFile):
line = tcl.format(f.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
class _VivadoProjectProperty:
def __init__(self, name=None, value=None, objects=None):
self.name = name
self.value = value
self.objects = objects
def emit(self):
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
hdlmake/vhdl_parser.py
View file @ d342f521
#!/usr/bin/python #!/usr/bin/python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
# #
# Copyright (c) 2013 CERN # Copyright (c) 2013-2015 CERN
# Author: Tomasz Wlostowski (tomasz.wlostowski@cern.ch) # Author:
# Tomasz Wlostowski (tomasz.wlostowski@cern.ch)
# Adrian Fiergolski (Adrian.Fiergolski@cern.ch)
# #
# This file is part of Hdlmake. # This file is part of Hdlmake.
# #
...@@ -22,142 +24,101 @@ ...@@ -22,142 +24,101 @@
from new_dep_solver import DepParser from new_dep_solver import DepParser
import logging import logging
import re
def _remove_gaps(buf, delims, gap_chars, lower_strings=False): class VHDLPreprocessor(object):
da = {}
for d in delims:
da[d] = False
prev_is_gap = False
buf2 = ""
lines = []
for c in buf:
for d in delims:
if c == d:
da[d] = not da[d]
within_string = any(da.values()) and not (c in delims) def __init__(self):
if not within_string: self.vhdl_file = None
if(c in gap_chars):
if(not prev_is_gap):
prev_is_gap = True
buf2 += " "
else:
prev_is_gap = False
buf2 += c
if c == ";" or c == "\n":
lines.append(buf2)
buf2 = ""
else:
buf2 += c
prev_is_gap = False
return lines
def remove_comments_and_strings(self, s):
pattern = re.compile( '--.*?$|".?"', re.DOTALL | re.MULTILINE )
return re.sub(pattern,"", s)
def _preporcess_file(self, file_content, file_name, library):
logging.debug("preprocess file %s (of length %d) in library %s" % (file_name, len(file_content), library) )
return self.remove_comments_and_strings(file_content)
def preprocess(self, vhdl_file):
self.vhdl_file = vhdl_file
file_path = vhdl_file.file_path
buf = open(file_path, "r").read()
return self._preporcess_file(file_content = buf, file_name = file_path, library = vhdl_file.library)
class VHDLParser(DepParser): class VHDLParser(DepParser):
def __init__(self, dep_file):
DepParser.__init__(self, dep_file)
self.preprocessor = VHDLPreprocessor()
def parse(self, dep_file): def parse(self, dep_file):
from dep_file import DepRelation from dep_file import DepRelation
if dep_file.is_parsed: if dep_file.is_parsed:
return return
logging.info("Parsing %s" % dep_file.path) logging.info("Parsing %s" % dep_file.path)
content = open(dep_file.file_path, "r")
buf = "" buf = self.preprocessor.preprocess(dep_file)
# stage 1: strip comments
for l in content.readlines(): #use packages
ci = l.find("--") use_pattern = re.compile("^\s*use\s+(\w+)\s*\.\s*(\w+)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
if ci == 0: def do_use(s) :
continue if ( s.group(1).lower() == "work" ) : #work is the current library in VHDL
logging.debug("use package %s.%s" % (dep_file.library, s.group(2) ) )
while ci > 0: dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(2).lower() ) , DepRelation.USE, DepRelation.PACKAGE))
quotes = l[:ci].count('"') # ignore comments in strings else :
if quotes % 2 == 0: logging.debug("use package %s.%s" % (s.group(1), s.group(2)) )
l = l[:ci-1] dep_file.add_relation(DepRelation("%s.%s" % (s.group(1).lower(), s.group(2).lower()), DepRelation.USE, DepRelation.PACKAGE))
break re.subn(use_pattern, do_use, buf)
ci = l.find("--", ci+1)
buf += l #new entity
entity_pattern = re.compile("^\s*entity\s+(\w+)\s+is\s+(?:port|generic|end)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
# stage 2: remove spaces, crs, lfs, strip strings (we don't need them) def do_entity(s) :
buf2 = "" logging.debug("found entity %s.%s" % ( dep_file.library, s.group(1) ) )
string_literal = char_literal = False dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(1).lower()),
prev_is_gap = False DepRelation.PROVIDE,
gap_chars = " \r\n\t" DepRelation.ENTITY))
lines = [] re.subn(entity_pattern, do_entity, buf)
for c in buf: #new package
if c == '"' and not char_literal: package_pattern = re.compile("^\s*package\s+(\w+)\s+is", re.DOTALL | re.MULTILINE | re.IGNORECASE )
string_literal = not string_literal def do_package(s) :
if c == "'" and not string_literal: logging.debug("found package %s.%s" % (dep_file.library, s.group(1) ))
char_literal = not char_literal dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(1).lower()),
DepRelation.PROVIDE,
within_string = (string_literal or char_literal) and (c != '"') and (c != "'") DepRelation.PACKAGE))
re.subn(package_pattern, do_package, buf)
if(not within_string):
if(c in gap_chars): #intantions
if(not prev_is_gap): instance_pattern = re.compile("^\s*(\w+)\s*\:\s*(\w+)\s*(?:port\s+map|generic\s+map|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
prev_is_gap = True instance_from_library_pattern = re.compile("^\s*(\w+)\s*\:\s*entity\s*(\w+)\s*\.\s*(\w+)\s*(?:port\s+map|generic\s+map|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
buf2 += " " libraries = set([dep_file.library])
else: def do_instance(s) :
prev_is_gap = False for lib in libraries :
buf2 += c.lower() logging.debug("-> instantiates %s.%s as %s" % (lib, s.group(2), s.group(1)) )
if c == ";": dep_file.add_relation(DepRelation("%s.%s" % (lib, s.group(2).lower()),
lines.append(buf2) DepRelation.USE,
buf2 = ""
else:
prev_is_gap = False
import re
patterns = {
"use": "^ *use +(\w+) *\. *(\w+) *\. *\w+ *;",
"entity": "^ *entity +(\w+) +is +(port|generic)",
"package": "^ *package +(\w+) +is",
"arch_begin": "^ *architecture +(\w+) +of +(\w+) +is +",
"arch_end": "^ *end +(\w+) +;",
"instance": "^ *(\w+) *\: *(\w+) *(port|generic) *map"
}
compiled_patterns = map(lambda p: (p, re.compile(patterns[p])), patterns)
within_architecture = False
for l in lines:
matches = filter(lambda (k, v): v is not None, map(lambda (k, v): (k, re.match(v, l)), compiled_patterns))
if(not len(matches)):
continue
what, g = matches[0]
if(what == "use"):
dep_file.add_relation(DepRelation(g.group(1)+"."+g.group(2), DepRelation.USE, DepRelation.PACKAGE))
if(what == "package"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
elif(what == "entity"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.ENTITY)) DepRelation.ENTITY))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)), def do_instance_from_library(s) :
DepRelation.PROVIDE, if ( s.group(2).lower() == "work" ) : #work is the current library in VHDL
logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, s.group(3), s.group(1)) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(3).lower()),
DepRelation.USE,
DepRelation.ENTITY)) DepRelation.ENTITY))
elif(what == "package"): else :
dep_file.add_relation(DepRelation(g.group(1), logging.debug("-> instantiates %s.%s as %s" % (s.group(2), s.group(3), s.group(1)) )
DepRelation.PROVIDE, dep_file.add_relation(DepRelation("%s.%s" % (s.group(2).lower(), s.group(3).lower()),
DepRelation.PACKAGE))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
elif(what == "arch_begin"):
arch_name = g.group(1)
within_architecture = True
elif(what == "arch_end" and within_architecture and g.group(1) == arch_name):
within_architecture = False
elif(what == "instance" and within_architecture):
dep_file.add_relation(DepRelation(g.group(2),
DepRelation.USE, DepRelation.USE,
DepRelation.ENTITY)) DepRelation.ENTITY))
dep_file.is_parsed = True re.subn(instance_pattern, do_instance, buf)
\ No newline at end of file re.subn(instance_from_library_pattern, do_instance_from_library, buf)
#libraries
library_pattern = re.compile("^\s*library\s*(\w+)\s*;", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_library(s) :
logging.debug("use library %s" % s.group(1))
libraries.add(s.group(1).lower())
re.subn(library_pattern, do_library, buf)
dep_file.is_parsed = True
hdlmake/vlog_parser.py
View file @ d342f521
...@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory ...@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory
class VerilogPreprocessor(object): class VerilogPreprocessor(object):
# Reserved verilog preprocessor keywords. The list is certainly not full
# Reserved verilog preprocessor keywords. The list is certainly not full
vpp_keywords = ["define", "line", "include", "elsif", "ifdef", "endif", "else", "undef", "timescale"] vpp_keywords = ["define", "line", "include", "elsif", "ifdef", "endif", "else", "undef", "timescale"]
# List of `include search paths # Verilog `define class
vpp_searchdir = ["."]
# List of macro definitions
vpp_macros = []
# Dictionary of files sub-included by each file parsed
vpp_filedeps = {}
# Verilog `define class
class VL_Define(object): class VL_Define(object):
def __init__(self, name, args, expansion): def __init__(self, name, args, expansion):
self.name = name self.name = name
...@@ -73,6 +65,13 @@ class VerilogPreprocessor(object): ...@@ -73,6 +65,13 @@ class VerilogPreprocessor(object):
def __init__(self): def __init__(self):
self.vpp_stack = self.VL_Stack() self.vpp_stack = self.VL_Stack()
self.vlog_file = None self.vlog_file = None
# List of `include search paths
self.vpp_searchdir = ["."]
# List of macro definitions
self.vpp_macros = []
# Dictionary of files sub-included by each file parsed
self.vpp_filedeps = {}
def _find_macro(self, name): def _find_macro(self, name):
for m in self.vpp_macros: for m in self.vpp_macros:
...@@ -137,7 +136,7 @@ class VerilogPreprocessor(object): ...@@ -137,7 +136,7 @@ class VerilogPreprocessor(object):
self.vpp_macros.append(mdef) self.vpp_macros.append(mdef)
return mdef return mdef
def _preprocess_file(self, file_content, file_name): def _preprocess_file(self, file_content, file_name, library):
exps = {"include": re.compile("^\s*`include\s+\"(.+)\""), exps = {"include": re.compile("^\s*`include\s+\"(.+)\""),
"define": re.compile("^\s*`define\s+(\w+)(?:\(([\w\s,]*)\))?(.*)"), "define": re.compile("^\s*`define\s+(\w+)(?:\(([\w\s,]*)\))?(.*)"),
"ifdef_elsif": re.compile("^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$"), "ifdef_elsif": re.compile("^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$"),
...@@ -145,11 +144,11 @@ class VerilogPreprocessor(object): ...@@ -145,11 +144,11 @@ class VerilogPreprocessor(object):
vl_macro_expand = re.compile("`(\w+)(?:\(([\w\s,]*)\))?") vl_macro_expand = re.compile("`(\w+)(?:\(([\w\s,]*)\))?")
# init dependencies # init dependencies
self.vpp_filedeps[file_name] = [] self.vpp_filedeps[file_name + library] = []
cur_iter = 0 cur_iter = 0
logging.debug("preprocess file %s (of length %d)" % (file_name, len(file_content))) logging.debug("preprocess file %s (of length %d) in library %s" % (file_name, len(file_content), library))
# print("BUF '%s'" %buf) # print("BUF '%s'" %buf)
buf = self._remove_comment(file_content) buf = self._remove_comment(file_content)
while True: while True:
...@@ -188,12 +187,12 @@ class VerilogPreprocessor(object): ...@@ -188,12 +187,12 @@ class VerilogPreprocessor(object):
if matches["include"]: if matches["include"]:
included_file_path = self._search_include(last.group(1), os.path.dirname(file_name)) included_file_path = self._search_include(last.group(1), os.path.dirname(file_name))
logging.debug("File being parsed %s includes %s" % (file_name, included_file_path)) logging.debug("File being parsed %s (library %s) includes %s" % (file_name, library, included_file_path))
line = self._preprocess_file(file_content=open(included_file_path, "r").read(), line = self._preprocess_file(file_content=open(included_file_path, "r").read(),
file_name=included_file_path) file_name=included_file_path, library=library)
self.vpp_filedeps[file_name].append(included_file_path) self.vpp_filedeps[file_name + library].append(included_file_path)
# add the whole include chain to the dependencies of the currently parsed file # add the whole include chain to the dependencies of the currently parsed file
self.vpp_filedeps[file_name].extend(self.vpp_filedeps[included_file_path]) self.vpp_filedeps[file_name + library].extend(self.vpp_filedeps[included_file_path + library])
new_buf += line + '\n' new_buf += line + '\n'
n_expansions += 1 n_expansions += 1
continue continue
...@@ -235,7 +234,7 @@ class VerilogPreprocessor(object): ...@@ -235,7 +234,7 @@ class VerilogPreprocessor(object):
self.vlog_file = vlog_file self.vlog_file = vlog_file
file_path = vlog_file.file_path file_path = vlog_file.file_path
buf = open(file_path, "r").read() buf = open(file_path, "r").read()
return self._preprocess_file(file_content=buf, file_name=file_path) return self._preprocess_file(file_content=buf, file_name=file_path, library = vlog_file.library)
def _find_first(self, f, l): def _find_first(self, f, l):
x = filter(f, l) x = filter(f, l)
...@@ -535,6 +534,7 @@ class VerilogParser(DepParser): ...@@ -535,6 +534,7 @@ class VerilogParser(DepParser):
return buf2 return buf2
def parse(self, dep_file): def parse(self, dep_file):
i = 0;
if dep_file.is_parsed: if dep_file.is_parsed:
return return
logging.info("Parsing %s" % dep_file.path) logging.info("Parsing %s" % dep_file.path)
...@@ -544,7 +544,7 @@ class VerilogParser(DepParser): ...@@ -544,7 +544,7 @@ class VerilogParser(DepParser):
#add includes as dependencies #add includes as dependencies
try: try:
includes = self.preprocessor.vpp_filedeps[dep_file.path] includes = self.preprocessor.vpp_filedeps[dep_file.path + dep_file.library]
for f in includes: for f in includes:
dep_file.depends_on.add(SourceFileFactory().new(path=f, module=dep_file.module)) dep_file.depends_on.add(SourceFileFactory().new(path=f, module=dep_file.module))
logging.debug( "%s has %d includes." % (str(dep_file), len(includes))) logging.debug( "%s has %d includes." % (str(dep_file), len(includes)))
...@@ -561,15 +561,15 @@ class VerilogParser(DepParser): ...@@ -561,15 +561,15 @@ class VerilogParser(DepParser):
#and HdlMake will anyway create dependency marking my_other_module as requested package #and HdlMake will anyway create dependency marking my_other_module as requested package
import_pattern = re.compile("(\w+) *::(\w+|\\*)") import_pattern = re.compile("(\w+) *::(\w+|\\*)")
def do_imports(s): def do_imports(s):
logging.debug("file %s imports/uses %s package" %( dep_file.path , s.group(1) ) ) logging.debug("file %s imports/uses %s.%s package" %( dep_file.path , dep_file.library, s.group(1) ) )
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.PACKAGE)) dep_file.add_relation( DepRelation( "%s.%s" % (dep_file.library, s.group(1)) , DepRelation.USE, DepRelation.PACKAGE))
re.subn(import_pattern, do_imports, buf) re.subn(import_pattern, do_imports, buf)
#packages #packages
m_inside_package = re.compile("package\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)endpackage", re.DOTALL | re.MULTILINE) m_inside_package = re.compile("package\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)endpackage", re.DOTALL | re.MULTILINE)
def do_package(s): def do_package(s):
logging.debug("found pacakge %s" %s.group(1)) logging.debug("found pacakge %s.%s" %(dep_file.library, s.group(1)) )
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.PACKAGE)) dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.PACKAGE))
re.subn(m_inside_package, do_package, buf) re.subn(m_inside_package, do_package, buf)
#modules and instatniations #modules and instatniations
...@@ -577,15 +577,15 @@ class VerilogParser(DepParser): ...@@ -577,15 +577,15 @@ class VerilogParser(DepParser):
m_instantiation = re.compile("(?:\A|\\s*)\s*(\w+)\s+(?:#\s*\(.*?\)\s*)?(\w+)\s*\(.*?\)\s*", re.DOTALL | re.MULTILINE) m_instantiation = re.compile("(?:\A|\\s*)\s*(\w+)\s+(?:#\s*\(.*?\)\s*)?(\w+)\s*\(.*?\)\s*", re.DOTALL | re.MULTILINE)
def do_module(s): def do_module(s):
logging.debug("found module %s" %s.group(1)) logging.debug("found module %s.%s" % (dep_file.library, s.group(1) ))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.ENTITY)) dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.ENTITY))
def do_inst(s): def do_inst(s):
mod_name = s.group(1) mod_name = s.group(1)
if(mod_name in self.reserved_words): if(mod_name in self.reserved_words):
return return
logging.debug("-> instantiates %s as %s" % (s.group(1), s.group(2) )) logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, s.group(1), s.group(2) ))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.ENTITY)) dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.USE, DepRelation.ENTITY))
re.subn(m_instantiation, do_inst, s.group(2)) re.subn(m_instantiation, do_inst, s.group(2))
re.subn(m_inside_module, do_module, buf) re.subn(m_inside_module, do_module, buf)
......
tests/counter/sim/iverilog/vhdl/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
files = [
"../../../modules/counter/vhdl/counter.vhd",
"../../../testbench/counter_tb/verilog/counter_tb.v",
]
tests/counter/sim/riviera/verilog/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "riviera"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
tests/counter/sim/riviera/vhdl/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "riviera"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
tests/counter/sim/riviera/vsim.do 0 → 100644
View file @ d342f521
vsim counter_tb +access +r;
add wave *;
run 6000ns;
tests/questa_uvm_sv/rtl/Manifest.py
View file @ d342f521
include_dirs = "./include" include_dirs = "./include"
files = ["include/includeModule.sv", files = ["include/includeModuleSV.sv",
"include/includeModuleVHDL.vhdl",
"include/includeModuleAVHDL.vhdl",
"include/includeModuleBVHDL.vhdl",
"RTL_SVPackage.sv", "RTL_SVPackage.sv",
"RTLTopModuleSV.sv", "RTLTopModuleSV.sv",
"RTLTopModuleVerilogSimulationModel.vo", "RTLTopModuleVerilogSimulationModel.vo",
......
tests/questa_uvm_sv/rtl/RTLTopModuleSV.sv
View file @ d342f521
...@@ -14,7 +14,7 @@ module RTLTopModuleSV; ...@@ -14,7 +14,7 @@ module RTLTopModuleSV;
initial initial
l1a <= RTL_SVPackage::CONST; l1a <= RTL_SVPackage::CONST;
includeModule incl(); includeModuleSV incl();
ipcore ip(); ipcore ip();
endmodule // RTLTopModuleSV endmodule // RTLTopModuleSV
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
View file @ d342f521
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL -- Title : RTLTopModuleVHDL Project :
-- Project :
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl -- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-- Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch>
-- Company : CERN
-- Created : 2014-09-26
-- Last update: 2014-09-26
-- Platform :
-- Standard : VHDL'2008
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: The module to test HDLMake -- Description: The module to test HDLMake
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN -- Copyright (c) 2014 CERN
-- --
-- This file is part of . -- This file is part of .
-- --
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License -- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
-- as published by the Free Software Foundation, either version 3 of the License, or any later version.
-- --
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-- --
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/. -- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-- Date Version Author Description
-- 2014-09-26 1.0 afiergol Created
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL; end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC; signal probe : STD_LOGIC;
begin -- architecture Behavioral begin -- architectureecture Behavioral
probe <= '1'; probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral; end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModuleAVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleAVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleAVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModuleBVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModule.sv → tests/questa_uvm_sv/rtl/include/includeModuleSV.sv
View file @ d342f521
// -*- Mode: Verilog -*- // -*- Mode: Verilog -*-
// Filename : includeModule.sv // Filename : includeModuleSV.sv
// Description : Included submodule // Description : Included submodule
// Author : Adrian Fiergolski // Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:51:41 2014 // Created On : Thu Sep 18 10:51:41 2014
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
// Update Count : 0 // Update Count : 0
// Status : Unknown, Use with caution! // Status : Unknown, Use with caution!
module includeModule; module includeModuleSV;
endmodule // includeModule endmodule // includeModuleSV
tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/sim/tests/Makefile
View file @ d342f521
...@@ -6,94 +6,121 @@ ...@@ -6,94 +6,121 @@
## variables ############################# ## variables #############################
PWD := $(shell pwd) PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/questa_sv_afv_10.3c_1/questasim//bin/.. MODELSIM_INI_PATH := /opt/questa_sv_afv_10.4/questasim//bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS := VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../rtl/RTL_SVPackage.sv \ VERILOG_SRC := ../../ipcores/ipcore/ipcore.sv \
../../rtl/include/includeModule.sv \ ../../rtl/RTL_SVPackage.sv \
../../ipcores/ipcore/ipcore.sv \
../../rtl/RTLTopModuleSV.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
src/genericTest.sv \ src/genericTest.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
../../rtl/include/includeModuleSV.sv \
../../rtl/RTLTopModuleSV.sv \
VERILOG_OBJ := work/RTL_SVPackage/.RTL_SVPackage_sv \ VERILOG_OBJ := work/ipcore/.ipcore_sv \
work/includeModule/.includeModule_sv \ work/RTL_SVPackage/.RTL_SVPackage_sv \
work/ipcore/.ipcore_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/genericTest/.genericTest_sv \ work/genericTest/.genericTest_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/includeModuleSV/.includeModuleSV_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
VHDL_SRC := ../../rtl/RTLTopModuleVHDL.vhdl \ VHDL_SRC := ../../rtl/include/includeModuleBVHDL.vhdl \
../../rtl/include/includeModuleVHDL.vhdl \
../../rtl/include/includeModuleAVHDL.vhdl \
../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_OBJ := work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \ VHDL_OBJ := work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl \
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/.work
## rules ################################# ## rules #################################
sim: sim_pre_cmd modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ) local: sim_pre_cmd simulation sim_post_cmd
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini $(VHDL_OBJ): $(LIB_IND) modelsim.ini
sim_pre_cmd: sim_pre_cmd:
sim_post_cmd: sim sim_post_cmd:
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
clean: clean:
rm -rf ./modelsim.ini $(LIBS) rm -rf ./modelsim.ini $(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd .PHONY: clean sim_pre_cmd sim_post_cmd simulation
work/.work: work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work (vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
@mkdir -p $(dir $@) && touch $@
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $< vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
work/includeModule/.includeModule_sv: ../../rtl/include/includeModule.sv work/genericTest/.genericTest_sv: src/genericTest.sv \
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $< ../environment/env.sv \
../sequences/sequence.sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
src/FullTest_pkg.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
../environment/top.sv \
../environment/Env_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \ work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
../../ipcores/ipcore/include/ipcoreInclude.sv vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $< @mkdir -p $(dir $@) && touch $@
work/includeModuleSV/.includeModuleSV_sv: ../../rtl/include/includeModuleSV.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \ work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \ work/ipcore/.ipcore_sv \
work/includeModule/.includeModule_sv \ work/includeModuleSV/.includeModuleSV_sv \
work/ipcore/.ipcore_sv work/RTL_SVPackage/.RTL_SVPackage_sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $< vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $< work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModuleBVHDL.vhdl
@mkdir -p $(dir $@) && touch $@ vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/genericTest/.genericTest_sv: src/genericTest.sv \ work/includeModuleVHDL/.includeModuleVHDL_vhdl: ../../rtl/include/includeModuleVHDL.vhdl
../sequences/sequence.sv \ vcom $(VCOM_FLAGS) -work work $<
../environment/Env_pkg.sv \ @mkdir -p $(dir $@) && touch $@
../environment/env.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
../environment/top.sv \
src/FullTest_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl: ../../rtl/include/includeModuleAVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl \
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
......
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