Add test for isim on windows, add missing files.

04a621c2 · Tristan Gingold · 5d176cdd · 04a621c2 · 04a621c2 · 04a621c2
Commit 04a621c2 authored Jun 11, 2019 by Tristan Gingold
9 changed files
--- a/testsuite/010isim/Manifest.py
+++ b/testsuite/010isim/Manifest.py
@@ -2,6 +2,8 @@ action = "simulation"

 sim_tool="isim"

+vlog_opt = "-i baddir"
+
 top_module = "gate3_tb"

 files = [ "../files/gate3.vhd", "../files/gate.vhdl", "../files/gate3_tb.v" ]
--- a/testsuite/025vlog_parser/unused.v
+++ b/testsuite/025vlog_parser/unused.v
+module unused;
+endmodule
--- a/testsuite/060isim_windows/Makefile.ref
+++ b/testsuite/060isim_windows/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+## variables #############################
+PWD := $(shell pwd)
+TOP_MODULE := gate3_tb
+FUSE_OUTPUT ?= isim_proj
+
+
+VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini 
+VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := ../files/gate3_tb.v \
+
+VERILOG_OBJ := work/gate3_tb/.gate3_tb_v \
+
+VHDL_SRC := ../files/gate.vhdl \
+../files/gate3.vhd \
+
+VHDL_OBJ := work/gate/.gate_vhdl \
+work/gate3/.gate3_vhd \
+
+LIBS := work
+LIB_IND := work\.work
+simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
+$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
+$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
+
+
+xilinxsim.ini: $(XILINX_INI_PATH)\xilinxsim.ini
+		copy $< .
+fuse:
+		fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
+
+
+work\.work:
+	(mkdir work && type nul >> work\.work && echo work=work  >> xilinxsim.ini) || del /s /q /f work 
+
+work/gate3_tb/.gate3_tb_v: ../files/gate3_tb.v ../files/gate3.vhd
+		vlogcomp -work work=.\work $(VLOGCOMP_FLAGS)  -i ../files $<
+		@mkdir $(dir $@) && type nul >> $@ 
+
+
+
+work/gate/.gate_vhdl: ../files/gate.vhdl work/gate/.gate
+		vhpcomp $(VHPCOMP_FLAGS) -work work=.\work $< 
+		@mkdir $(dir $@) && type nul >> $@
+
+
+work/gate/.gate:
+		@mkdir $(dir $@) && type nul >> $@
+
+work/gate3/.gate3_vhd: ../files/gate3.vhd work/gate3/.gate3
+		vhpcomp $(VHPCOMP_FLAGS) -work work=.\work $< 
+		@mkdir $(dir $@) && type nul >> $@
+
+
+work/gate3/.gate3: \
+work/gate/.gate_vhdl
+		@mkdir $(dir $@) && type nul >> $@
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb isim_proj isim_proj.*
+
+clean:
+		del /s /q /f $(CLEAN_TARGETS)
+		@-rmdir /s /q $(CLEAN_TARGETS) >nul 2>&1
+mrproper: clean
+		del /s /q /f *.vcd
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/060isim_windows/Manifest.py
+++ b/testsuite/060isim_windows/Manifest.py
+action = "simulation"
+
+sim_tool="isim"
+
+top_module = "gate3_tb"
+
+files = [ "../files/gate3.vhd", "../files/gate.vhdl", "../files/gate3_tb.v" ]
--- a/testsuite/files/gate3.vhd
+++ b/testsuite/files/gate3.vhd
+entity gate3 is
+  port (i : in bit;
+        o : out bit);
+end gate3;
+
+architecture behav of gate3 is
+begin
+  inst: entity work.gate 
+    port map (i, o);
+end behav;
--- a/testsuite/files/gate3_tb.v
+++ b/testsuite/files/gate3_tb.v
+module gate3_tb;
+  reg i, o;
+  gate3 dut(.i(i), .o(o));
+  initial begin
+    i <= 0;
+    # 1;
+    $stop;
+  end
+endmodule
--- a/testsuite/no_fakebin/empty
+++ b/testsuite/no_fakebin/empty
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -9,15 +9,16 @@ import pytest
 import shutil

 class Config(object):
-    def __init__(self, path=None, check_windows=False):
+    def __init__(self, path=None, check_windows=False, fakebin="linux_fakebin"):
        self.path = path
        self.prev_env_path = os.environ['PATH']
        self.prev_check_windows = hdlmake.util.shell.check_windows
        self.check_windows = check_windows
+        self.fakebin = fakebin

    def __enter__(self):
-        os.environ['PATH'] = ("../linux_fakebin:"
-            + os.path.abspath('linux_fakebin') + ':'
+        os.environ['PATH'] = ("../" + self.fakebin + ":"
+            + os.path.abspath(self.fakebin) + ':'
            + self.prev_env_path)
        if self.path is not None:
            os.chdir(self.path)
@@ -35,6 +36,13 @@ def compare_makefile():
    assert out == ref
    os.remove('Makefile')

+def compare_makefile_xilinx():
+    ref = open('Makefile.ref', 'r').readlines()
+    out = open('Makefile', 'r').readlines()
+    # HDLmake make the path absolute.  Remove this line.
+    out = [l for l in out if not l.startswith("XILINX_INI_PATH")]
+    assert out == ref
+    os.remove('Makefile')

 def run_compare(**kwargs):
    with Config(**kwargs) as _:
@@ -90,12 +98,13 @@ def test_icestorm():
 def test_isim():
    with Config(path="010isim") as _:
        hdlmake.__main__.hdlmake([])
-        ref = open('Makefile.ref', 'r').readlines()
-        out = open('Makefile', 'r').readlines()
-        # HDLmake make the path absolute.  Remove this line.
-        out = [l for l in out if not l.startswith("XILINX_INI_PATH")]
-        assert out == ref
-        os.remove('Makefile')
+        compare_makefile_xilinx()
+
+def test_isim_windows():
+    with Config(path="060isim_windows",
+                check_windows=True, fakebin="windows_fakebin") as _:
+        hdlmake.__main__.hdlmake([])
+        compare_makefile_xilinx()

 def test_icarus():
    run_compare(path="012icarus")

--- a/testsuite/windows_fakebin/isimgui.exe
+++ b/testsuite/windows_fakebin/isimgui.exe