Add macro-based dpram for Xilinx/AMD 7Series FPGA

Hi,

this MR adds a new dpram implementation which is backed by the VHDL macro for 7Series FPGAs. (--> https://docs.xilinx.com/r/en-US/ug953-vivado-7series-libraries/BRAM_TDP_MACRO)

Various datawidths are supported and if the depth of a single 18kbit or 36kbit BRAM is not sufficient, multiple BRAMs are instantiated. These BRAM blocks can be updated after bitstream generation by using external tools such as the updatemem command.

Looking forward to your feedback!