gc argb led drv

See merge request !67

Add macro-based dpram for Xilinx/AMD 7Series FPGA

See merge request !66

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

add -min argument to get_property PERIOD to return the minimum value of the returned list

See merge request !65

Fix to CDC constraints generator matching filters

See merge request !43

Resolve "Linux driver for wb simple uart"

See merge request !62

Driver for the simple wb UART. It supports only physical UART.
Signed-off-by: Piotr Klasa <piotr.klasa@cern.ch>

Resolve "Support Verilog output with gen_sourceid tool"

See merge request !63

Also make it possible to define the name of the project with a
command-line argument.

Resolve "add rx/tx interrupt enable in wb_uart"

See merge request !58

Resolve "add a fifo with mixed width"

See merge request !57

Create branch wb_axi_bridge_fix and add fix for wb - axi4 lite bridge

See merge request !60

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Resolve "fifo: minor cleanup"

See merge request !56

Add comments, remove components, add some default to the generics
No functional changes

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Addition of 2 bits in status register to clarify if you are using Virtual or Physical UART

See merge request !53

Addition of the generated file wb_uart_regs.vh and changes in the comments of the new registers for PHYSICAL/VIRTUAL UART

update CHANGELOG sw changes

See merge request !50

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

modules/axi: add mpsoc_int_gen (to generate pcie interrupts)

See merge request !47

fix: improve filtering to include prefixed sync_word and multi-aasd

See merge request !46

fix: skip constraints gen for optimized out destination pins

See merge request !45