hdl/sim: Protect CIWBMasterAccessor against multiple requests
When performing reads/writes from multiple threads, CIWBMasterAccessor does not provide any protection, leading to data from one request being delivered to another. By replacing the data queues with SV mailboxes, we ensure that only one thread can access the mailbox at any given time. Furthermore, we add a SV event in wb_cycle_t, which is used to notify the readm()/writem() tasks that their transfer is complete, to avoid getting the result of the wrong transfer.
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