Commit 7dd450ae authored by kblantos's avatar kblantos

Adding Testbench for AXI cores

parent 074d4468
action="simulation"
sim_tool="ghdl"
target="generic"
ghdl_opt="--std=08 -frelaxed-rules"
sim_top="tb_axi4lite32_axi4full64_bridge"
files="tb_axi4lite32_axi4full64_bridge.vhd"
modules={"local" : ["../../../",
"../../../modules/wishbone",
"../../../modules/axi"]}
## Description
Testbench for [axi4lite32_axi4full64_bridge](../../modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd) which is a bridge from AXI4Lite32 to AXI4Full64. Master is the axi4lite and the slave is axi4full.
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument to this script:
```console
./run.sh <simulation time>
```
#!/bin/bash -e
#This is a simple script to run simulations in GHDL
TB=tb_axi4lite32_axi4full64_bridge
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
action ="simulation"
sim_tool="ghdl"
target ="generic"
ghdl_opt="--std=08 -frelaxed-rules"
sim_top ="tb_axi4lite_axi4full_bridge"
files ="tb_axi4lite_axi4full_bridge.vhd"
modules = {"local" : ["../../../",]}
## Description
Testbench for [axi4lite_axi4full_bridge](../../modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd) which is a bridge from AXI4Lite to AXI4Full. Master is the axi4lite and the slave is axi4full.
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument (integer) to this script:
```console
./run.sh <simulation time>
```
#!/bin/bash -e
#This is a simple script to run simulations in GHDL
TB=tb_axi4lite_axi4full_bridge
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
action="simulation"
sim_tool="ghdl"
target="generic"
ghdl_opt="--std=08 -frelaxed-rules"
sim_top="tb_xaxi4lite_wb_bridge"
files="tb_xaxi4lite_wb_bridge.vhd"
modules={"local" : ["../../../",
"../../../modules/wishbone",
"../../../modules/axi"]}
## Description
Testbench for [axi4lite_wb_bridge](../../modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd) which is a bridge from AXI4 Lite to Wishbone. In this core, the Master is AXI4 Lite and Slave is Wishbone.
NOTE: By default, the simulation time is 4ms. To change this, run the test and pass the simulation time as an argument (integer) to this script:
```console
./run.sh <simulation time>
```
#!/bin/bash -e
#This is a simple script to run simulations in GHDL
TB=tb_xaxi4lite_wb_bridge
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
This diff is collapsed.
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
target = "xilinx"
action = "simulation"
sim_tool = "ghdl" #"modelsim"
top_module = "sim_top_ps_gpio"
syn_device = "XC7Z010"
# This can be deleted when GHDL not used
ghdl_opt = "--std=08 -frelaxed-rules"
files = [ "gpio_axi.vhd", "sim_top_ps_gpio.vhd" ]
......
#!/bin/bash -e
#This is a simple script to run simulations in GHDL
TB=sim_top_ps_gpio
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB
echo "********************************************"
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