Skip to content

P
Platform-independent core collection
Commit 66de3f0f authored by kblantos's avatar kblantos
Browse files
Options

README of AXI testbench changed. Also, now the user can change the simulation… 

README of AXI testbench changed. Also, now the user can change the simulation time before running the test
parent 9dcde218
Hide whitespace changes
Inline Side-by-side
Showing with 55 additions and 23 deletions
testbench/axi/axi4lite32_axi4full64_bridge/README.md
View file @ 66de3f0f
## Description
This is a testbench in order to verify the behavior of the axi4lite 32-bits to axi4full 64-bits, bridge [axi4lite32_axi4full64_bridge](../../modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd). Master is the axi4lite and the slave is axi4full.
NOTE: You can change the simulation time by changing the NOW variable in the stimulus
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument to this script:
```console
./run.sh <simulation time>
```
testbench/axi/axi4lite32_axi4full64_bridge/run.sh
View file @ 66de3f0f
......@@ -4,7 +4,12 @@
TB=tb_axi4lite32_axi4full64_bridge
echo "Running simulation for $TB"
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
View file @ 66de3f0f
......@@ -41,7 +41,8 @@ use osvvm.CoveragePkg.all;
entity tb_axi4lite32_axi4full64_bridge is
generic (
g_seed : natural);
g_seed : natural;
g_sim_time : natural);
end entity;
--==============================================================================
......@@ -55,6 +56,7 @@ architecture tb of tb_axi4lite32_axi4full64_bridge is
--==========================================================
constant C_CLK_PERIOD : time := 10 ns;
constant C_SIM_TIME : time := (g_sim_time*1.0 ms);
constant RSP_OKAY : std_logic_vector(1 downto 0) := b"00";
constant RSP_EXOKAY : std_logic_vector(1 downto 0) := b"01";
constant RSP_SLVERR : std_logic_vector(1 downto 0) := b"10";
......@@ -294,7 +296,7 @@ begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i = '1';
while (NOW < 4 ms) loop
while (NOW < C_SIM_TIME) loop
wait until rising_edge(tb_clk_i);
-- AXI-4 Full inputs
tb_s_awaddr <= data.randSlv(32);
......
testbench/axi/axi4lite_axi4full_bridge/README.md
View file @ 66de3f0f
## Description
This is a testbench in order to verify the behavior of the axi4lite to axi4full bridge [axi4lite_axi4full_bridge](../../modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd). Master is the axi4lite and the slave is axi4full.
NOTE: You can change the simulation time by changing the NOW variable in the stimulus of the test
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument (integer) to this script:
```console
./run.sh <simulation time>
```
testbench/axi/axi4lite_axi4full_bridge/run.sh
View file @ 66de3f0f
......@@ -4,7 +4,13 @@
TB=tb_axi4lite_axi4full_bridge
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM --wave=waveform.ghw
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
View file @ 66de3f0f
......@@ -42,6 +42,7 @@ use osvvm.CoveragePkg.all;
entity tb_axi4lite_axi4full_bridge is
generic (
g_seed : natural;
g_sim_time : natural;
g_ADDR_WIDTH : natural := 32;
g_DATA_WIDTH : natural := 32;
g_ID_WIDTH : natural := 4;
......@@ -60,6 +61,7 @@ architecture tb of tb_axi4lite_axi4full_bridge is
--==========================================================
constant C_CLK_PERIOD : time := 10 ns;
constant C_SIM_TIME : time := (g_sim_time*1.0 ms);
-- Used for FSM coverage
constant RSP_OKAY : std_logic_vector(1 downto 0) := b"00";
constant RSP_EXOKAY : std_logic_vector(1 downto 0) := b"01";
......@@ -133,12 +135,12 @@ architecture tb of tb_axi4lite_axi4full_bridge is
signal stop : boolean;
signal waddr : std_logic_vector(g_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal s_wlen : std_logic_vector(g_LEN_WIDTH-1 downto 0) := (others=>'0');
signal s_wsize : std_logic_vector(2 downto 0);
signal s_raddr : std_logic_vector(g_ADDR_WIDTH-1 downto 0);
signal s_rlen : std_logic_vector(g_LEN_WIDTH-1 downto 0);
signal s_wlen : std_logic_vector(g_LEN_WIDTH-1 downto 0) := (others=>'0');
signal s_wsize : std_logic_vector(2 downto 0) ;
signal s_raddr : std_logic_vector(g_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal s_rlen : std_logic_vector(g_LEN_WIDTH-1 downto 0) := (others=>'0');
signal s_rsize : std_logic_vector(2 downto 0);
signal s_rdata : std_logic_vector(g_DATA_WIDTH-1 downto 0);
signal s_rdata : std_logic_vector(g_DATA_WIDTH-1 downto 0) := (others=>'0');
signal s_awvalid : std_logic;
signal s_wvalid : std_logic;
signal s_wstrb : std_logic_vector((g_DATA_WIDTH/8)-1 downto 0);
......@@ -309,7 +311,7 @@ begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i = '1';
while (NOW < 1 ms) loop
while (NOW < C_SIM_TIME) loop
wait until rising_edge(tb_clk_i);
-- AXI-4 Full inputs
tb_s_awaddr <= data.randSlv(g_ADDR_WIDTH);
......
testbench/axi/axi4lite_wb_bridge/README.md
View file @ 66de3f0f
......@@ -2,4 +2,7 @@
This is the testbench for the AXI4 Lite to Wishbone bridge core [axi4lite_wb_bridge](../../modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd).
In this core, the Master is AXI4 Lite and Slave is Wishbone.
NOTE: You can change the simulation time by changing the NOW variable in the stimulus
NOTE: By default, the simulation time is 4ms. To change this, run the test and pass the simulation time as an argument (integer) to this script:
```console
./run.sh <simulation time>
```
testbench/axi/axi4lite_wb_bridge/run.sh
View file @ 66de3f0f
......@@ -4,8 +4,14 @@
TB=tb_xaxi4lite_wb_bridge
if [ -z "$1" ]; then
TIME="4"
else
TIME="$1"
fi;
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM --wave=waveform.ghw
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
testbench/axi/axi4lite_wb_bridge/tb_xaxi4lite_wb_bridge.vhd
View file @ 66de3f0f
......@@ -8,7 +8,7 @@
-- Platform : FPGA-generics
-- Standard : VHDL '08
-------------------------------------------------------------------------------
-- Description:
-- Description:
--
-- Testbench for a WB Slave Classic to AXI4-Lite Master bridge.
-------------------------------------------------------------------------------
......@@ -38,13 +38,15 @@ use osvvm.CoveragePkg.all;
entity tb_xaxi4lite_wb_bridge is
generic (
g_seed : natural);
g_seed : natural;
g_sim_time : natural);
end entity;
architecture tb of tb_xaxi4lite_wb_bridge is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
constant C_SIM_TIME : time := (g_sim_time*1.0 ms);
-- Signals
signal tb_clk_i : std_logic;
......@@ -55,14 +57,14 @@ architecture tb of tb_xaxi4lite_wb_bridge is
signal tb_axi4_master_i : t_axi4_lite_master_in_32;
signal stop : boolean;
signal s_araddr : std_logic_vector(31 downto 0);
signal s_araddr : std_logic_vector(31 downto 0);
signal s_wb_data : std_logic_vector(31 downto 0);
type t_state is (IDLE, READ, WRITE, WB_END);
signal s_state : t_state;
shared variable sv_cover : covPType;
--------------------------------------------------------------------------------
-- Procedures used for fsm coverage
--------------------------------------------------------------------------------
......@@ -139,7 +141,7 @@ begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i = '1';
while (NOW < 2 ms) loop
while (NOW < C_SIM_TIME) loop
wait until rising_edge(tb_clk_i);
-- Slave inputs
tb_wb_slave_i.cyc <= data.randSlv(1)(1);
......@@ -280,7 +282,7 @@ begin
end loop;
wait;
end process;
-- Check wb and axi4lite signals when READ
process
......@@ -300,13 +302,13 @@ begin
s_wb_data <= tb_axi4_master_i.RDATA;
wait for 1 ns;
assert (tb_wb_slave_o.dat = s_wb_data)
report "WB slave output data mismatch" severity failure;
report "WB slave output data mismatch" severity failure;
assert (tb_wb_slave_o.ack = '1' AND tb_wb_slave_o.err = '0')
report "Wrong ACK and ERR for specific RRESP" severity failure;
elsif tb_axi4_master_i.RVALID = '1' then
wait for 1 ns;
assert (tb_wb_slave_o.ack = '0' AND tb_Wb_slave_o.err = '1')
report "Wrong ACK and ERR" severity failure;
report "Wrong ACK and ERR" severity failure;
else
s_wb_data <= (others=>'0');
assert (tb_wb_slave_o.ack = '0' AND tb_Wb_slave_o.err = '0')
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment