Fix reset CDC issue in gc_sync_word_rd

The clk_out domain mistakenly used reset from clk_in domain. Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.

Fix reset CDC issue in gc_sync_word_rd
The clk_out domain mistakenly used reset from clk_in domain. Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.
561d2f72 · Adrian Byszuk · a68a932b · 561d2f72
Commit 561d2f72 authored Sep 28, 2021 by Adrian Byszuk
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Showing with 8 additions and 5 deletions

gc_sync_word_rd.vhd modules/common/gc_sync_word_rd.vhd +8 -5

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--- a/modules/common/gc_sync_word_rd.vhd
+++ b/modules/common/gc_sync_word_rd.vhd
@@ -67,6 +67,7 @@ architecture arch of gc_sync_word_rd is
  signal d_ready : std_logic;
  signal wr_in   : std_logic;
  signal rd_out  : std_logic;
+
 begin
  cmp_pulse_sync : entity work.gc_pulse_synchronizer2
    port map (
@@ -88,18 +89,20 @@ begin
    end if;
  end process;

-  p_writer : process (clk_out_i)
+  p_writer : process(clk_out_i)
  begin
    if rising_edge(clk_out_i) then
-      if rst_in_n_i = '0' then
-        ack_out_o <= '0';
-      elsif wr_in = '1' then
+      if wr_in = '1' then
        --  Data is stable.
        data_out_o <= gc_sync_word_data;
-        ack_out_o    <= '1';
+        ack_out_o  <= '1';
      else
        ack_out_o <= '0';
      end if;
+
+      if rst_out_n_i = '0' then
+        ack_out_o <= '0';
+      end if;
    end if;
  end process;
 end arch;