radtol: more fixes

3f5fa5e9 · Tristan Gingold · 9d62248e · 3f5fa5e9 · 3f5fa5e9
Commit 3f5fa5e9 authored Dec 15, 2021 by Tristan Gingold
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Showing with 26 additions and 21 deletions

secded_32b_pkg.vhd modules/radtol/secded_32b_pkg.vhd +6 -2

tb_secded_32b_pkg.vhd testbench/radtol/tb_secded_32b_pkg.vhd +20 -19

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--- a/modules/radtol/secded_32b_pkg.vhd
+++ b/modules/radtol/secded_32b_pkg.vhd
@@ -43,7 +43,7 @@ package secded_32b_pkg is
  function f_ecc_one_error (syndrome : ecc_word_t) return std_logic;

  --  Fix the error (if any).
-  --  Returns new ecc + new data.
+  --  Returns new ecc + data, from syndrome and original ecc + data.
  function f_fix_error (syndrome : ecc_word_t;
                        ecc : ecc_word_t;
                        data : data_word_t) return std_logic_vector;
@@ -119,6 +119,10 @@ package body secded_32b_pkg is
    end loop;

    --  Return the fixed ecc+data.
-    return (syndrome xor ecc) & (result xor data);
+    if result /= (data_word_t'range => '0') then
+      return ecc & (data xor result);
+    else
+      return (syndrome xor ecc) & (data xor result);
+    end if;
  end f_fix_error;
 end secded_32b_pkg;
--- a/testbench/radtol/tb_secded_32b_pkg.vhd
+++ b/testbench/radtol/tb_secded_32b_pkg.vhd
@@ -21,45 +21,46 @@ architecture behav of tb_secded_32b_pkg is
    return res;
  end image;

-  signal data, err, data2 : std_logic_vector (31 downto 0);
-  signal ecc, ecc2, syndrome : std_logic_vector(6 downto 0);
-  signal cor : std_logic_vector(38 downto 0);
+  signal orig_data, data : std_logic_vector (31 downto 0);
+  signal orig_ecc, ecc, comp_ecc, syndrome : std_logic_vector(6 downto 0);
+  signal err, cor : std_logic_vector(38 downto 0);
 begin
  process
  begin
-    data <= x"789a_d3f5";
+    orig_data <= x"789a_d3f5";
    syndrome <= "0000000";
    wait for 1 ns;
    assert f_ecc_errors (syndrome) = '0' severity failure;
    assert f_ecc_one_error (syndrome) = '0' severity failure;
-    ecc <= f_calc_ecc (data);
+    orig_ecc <= f_calc_ecc (orig_data);

    --  Single error (detection and correction)
    for i in 0 to 38 loop
      err <= (others => '0');
+      err (i) <= '1';
+      wait for 1 ns;
      if i < 32 then
-        err (i) <= '1';
-        wait for 1 ns;
-        data2 <= data xor err;
-        wait for 1 ns;
-        ecc2 <= f_calc_ecc (data2);
+        --  Bit flip in data
+        data <= orig_data xor err(31 downto 0);
+        ecc <= orig_ecc;
      else
-        err (i - 32) <= '1';
-        wait for 1 ns;
-        ecc2 <= ecc xor err(6 downto 0);
-        data2 <= data;
+        --  Bit flip in ecc
+        ecc <= orig_ecc xor err(38 downto 32);
+        data <= orig_data;
      end if;
      wait for 1 ns;
-      syndrome <= ecc2 xor ecc;
+      comp_ecc <= f_calc_ecc (data);
+      wait for 1 ns;
+      syndrome <= comp_ecc xor ecc;
      wait for 1 ns;
      assert f_ecc_errors (syndrome) = '1' severity failure;
      assert f_ecc_one_error (syndrome) = '1' severity failure;
-      cor <= f_fix_error(syndrome, ecc2, data2);
+      cor <= f_fix_error(syndrome, ecc, data);
      wait for 1 ns;
-      report "data:  " & image (data) & ", ecc:  " & image (ecc) & ", err: " & image (err) & ", ecc/err: " & image(ecc2);
+      report "data:  " & image (data) & ", ecc:  " & image (ecc) & ", err: " & image (err) & ", ecc/err: " & image(comp_ecc);
      report "cdata: " & image (cor(31 downto 0)) & ", cecc: " & image(cor(38 downto 32)) & " syndrome: " & image(syndrome);
-      assert cor(31 downto 0) = data severity failure;
-      assert cor(38 downto 32) = ecc severity failure;
+      assert cor(31 downto 0) = orig_data severity failure;
+      assert cor(38 downto 32) = orig_ecc severity failure;
    end loop;
    report "end of test";
    wait;