Merge branch '42-improve-timing-for-acam-tdc-start01-readout' into 'master'

Resolve "Improve timing for ACAM TDC START01 readout" Closes #42 See merge request be-cem-edl/fec/hardware-modules/fmc-tdc-1ns-5cha!21

Merge branch '42-improve-timing-for-acam-tdc-start01-readout' into 'master'
Resolve "Improve timing for ACAM TDC START01 readout" Closes #42 See merge request be-cem-edl/fec/hardware-modules/fmc-tdc-1ns-5cha!21
724b0f91 · Dimitris Lampridis · d1cac3b5 · 70d14c33 · 724b0f91
Commit 724b0f91 authored Aug 31, 2023 by Dimitris Lampridis
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reg_ctrl.vhd hdl/rtl/reg_ctrl.vhd +4 -1

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--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -130,6 +130,7 @@ architecture rtl of reg_ctrl is

  signal acam_config                     : config_vector;
  signal reg_adr, reg_adr_pipe0          : std_logic_vector(7 downto 0);
+  signal acam_start01_pipe0              : std_logic_vector(g_width-1 downto 0);
  signal starting_utc, acam_inputs_en    : std_logic_vector(g_width-1 downto 0);
  signal ctrl_reg, ctrl_reg_d            : std_logic_vector(g_width-1 downto 0);
  signal irq_tstamp_threshold            : std_logic_vector(g_width-1 downto 0);
@@ -455,6 +456,8 @@ begin
      dat_out_pipe2 <= dat_out_comb2;
      dat_out_pipe3 <= dat_out_comb3;
      wb_out.dat    <= dat_out_pipe0 or dat_out_pipe1 or dat_out_pipe2 or dat_out_pipe3;
+      -- added for easier timing closure
+      acam_start01_pipe0 <= acam_start01_i;
    --end if;
    end if;
  end process;
@@ -490,7 +493,7 @@ begin
    x"00000000"           when others;

  with reg_adr_pipe0 select dat_out_comb2 <=
-    acam_start01_i         when c_ACAM_REG10_RDBK_ADR,
+    acam_start01_pipe0     when c_ACAM_REG10_RDBK_ADR,
    acam_config_rdbk_i(8)  when c_ACAM_REG11_RDBK_ADR,
    acam_config_rdbk_i(9)  when c_ACAM_REG12_RDBK_ADR,
    acam_config_rdbk_i(10) when c_ACAM_REG14_RDBK_ADR,