hdl: fix wrong reset logic for control register

0cf850c5 · Dimitris Lampridis · f3a3e73c · 0cf850c5
Commit 0cf850c5 authored Dec 16, 2022 by Dimitris Lampridis
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reg_ctrl.vhd hdl/rtl/reg_ctrl.vhd +1 -1

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--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -398,7 +398,7 @@ begin
  process (clk_tdc_i)
  begin
    if rising_edge (clk_tdc_i) then
-      if rst_tdc_n_i = '1' then
+      if rst_tdc_n_i = '0' then
        ctrl_reg_d <= (others =>'0');
      else
        ctrl_reg_d <= ctrl_reg;